Source-Opened RISCV for Crypto
☆18Jan 18, 2022Updated 4 years ago
Alternatives and similar repositories for soric_project
Users that are interested in soric_project are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RV64IMAC modelling using System Verilog HDL☆24Aug 10, 2024Updated last year
- Open source tools for IC design☆13Dec 12, 2024Updated last year
- ☆15Jul 14, 2024Updated last year
- I2C master/slave Core☆15Jul 17, 2014Updated 11 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆34Dec 25, 2025Updated 2 months ago
- Build script to compile an up-to-date RISC-V GCC toolchain on Debian / Ubuntu with rv32e, rv32i and rv64i architectures and ilp32e, ilp3…☆11Aug 5, 2025Updated 7 months ago
- Embedded UVM (D Language port of IEEE UVM 1.0)☆34Nov 6, 2025Updated 4 months ago
- APB master and slave developed in RTL.☆23Oct 25, 2025Updated 4 months ago
- Elgamal's over Elliptic Curves☆20Dec 22, 2018Updated 7 years ago
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆26Aug 16, 2023Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆124Jul 22, 2021Updated 4 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆17Sep 2, 2023Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆24Feb 16, 2022Updated 4 years ago
- VLSI placement and routing tool☆15Dec 20, 2025Updated 3 months ago
- Primitives for GF180MCU provided by GlobalFoundries.☆56Aug 28, 2023Updated 2 years ago
- ☆37Mar 7, 2026Updated 2 weeks ago
- PyTorch utilities to handle the KITTI Vision Benchmark Suite☆11Jul 21, 2022Updated 3 years ago
- gaw3-20200922 fork with patches to improve remote commands sent from xschem to display waveforms☆17Mar 28, 2025Updated 11 months ago
- The OpenPiton Platform☆28May 22, 2023Updated 2 years ago
- LAYout with Gridded Objects☆32Jun 18, 2020Updated 5 years ago
- fork from svn @ http://code.google.com/p/prettytable/☆11Oct 11, 2012Updated 13 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Mar 5, 2019Updated 7 years ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- ☆24Feb 22, 2024Updated 2 years ago
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆26Sep 8, 2024Updated last year
- 国产全志平头哥C906 RISC-V DongshanPI-D1s RV64GVC 裸机示例仓库！☆16May 9, 2024Updated last year
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆91Jul 29, 2019Updated 6 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Nov 18, 2024Updated last year
- Command-line utility to return Zotero record field values given a Zotero select link, an item key, or even just a file attachment☆10Dec 23, 2023Updated 2 years ago
- Implementation of BitonicSorting algorithm on FPGA through SDAccel using Opencl as source code☆17Nov 21, 2016Updated 9 years ago
- I2C slave Verilog Design and TestBench☆27May 9, 2019Updated 6 years ago
- The code repository of DGCNN on FPGA: Acceleration of The Point Cloud Classifier Using FPGAs☆17Mar 6, 2023Updated 3 years ago
- ☆19Oct 28, 2024Updated last year
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆38Jun 2, 2021Updated 4 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 2 years ago
- ZCU102 two IMX274 camera design.☆12Feb 3, 2023Updated 3 years ago
- A mixed-signal system on chip for nanopore-based DNA sequencing☆36Nov 30, 2022Updated 3 years ago
- ☆19Jul 12, 2024Updated last year