phthinh / soric_projectLinks
Source-Opened RISCV for Crypto
☆16Updated 3 years ago
Alternatives and similar repositories for soric_project
Users that are interested in soric_project are comparing it to the libraries listed below
Sorting:
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Updated 3 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆20Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- ☆37Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 weeks ago
- ☆17Updated 8 months ago
- Demo SoC for SiliconCompiler.☆59Updated last month
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated last week
- FPGA250 aboard the eFabless Caravel☆30Updated 4 years ago
- Extended and external tests for Verilator testing☆16Updated this week
- ☆33Updated 2 years ago
- An Open Source Link Protocol and Controller☆25Updated 3 years ago
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago
- Xilinx Unisim Library in Verilog☆78Updated 4 years ago
- RISC-V soft-core PEs for TaPaSCo☆22Updated last year
- Cross EDA Abstraction and Automation☆39Updated this week
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Updated 2 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Updated last year
- Platform Level Interrupt Controller☆41Updated last year
- ☆30Updated this week
- LIS Network-on-Chip Implementation☆30Updated 8 years ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- Wishbone SATA Controller☆18Updated last month
- APB Logic☆18Updated 7 months ago
- Virtual development board for HDL design☆42Updated 2 years ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Updated last year