phthinh / soric_projectLinks
Source-Opened RISCV for Crypto
☆18Updated 3 years ago
Alternatives and similar repositories for soric_project
Users that are interested in soric_project are comparing it to the libraries listed below
Sorting:
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 3 months ago
- FPGA250 aboard the eFabless Caravel☆31Updated 4 years ago
- ☆18Updated 5 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆14Updated 6 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 5 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Demo SoC for SiliconCompiler.☆61Updated this week
- ☆38Updated 3 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 10 months ago
- ☆17Updated 11 months ago
- An open source PDK using TIGFET 10nm devices.☆51Updated 2 years ago
- ☆54Updated 6 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- LIS Network-on-Chip Implementation☆31Updated 9 years ago
- Cross EDA Abstraction and Automation☆39Updated this week
- ☆60Updated 4 years ago
- ☆32Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- ☆29Updated 2 weeks ago
- ☆32Updated 9 months ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆66Updated 11 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 11 months ago
- Extended and external tests for Verilator testing☆16Updated 3 weeks ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆37Updated this week
- FPGA reference design for the the Swerv EH1 Core☆72Updated 5 years ago