Source-Opened RISCV for Crypto
☆18Jan 18, 2022Updated 4 years ago
Alternatives and similar repositories for soric_project
Users that are interested in soric_project are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Ibex RISC-V core extended with hardware acceleration of cryptography functions☆14May 10, 2024Updated 2 years ago
- Open source tools for IC design☆18Aug 4, 2026Updated 2 months ago
- RV64IMAC modelling using System Verilog HDL☆28Aug 15, 2026Updated 2 months ago
- ☆17Jul 14, 2024Updated 2 years ago
- Random Embedding and Multi-objective Trust-region Bayesian Optimization for VLSI Flow Parameter Tuning☆11Dec 21, 2024Updated last year
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Disguising Attacks with Explanation-Aware Backdoors (IEEE S&P 2023)☆13Jan 3, 2026Updated 9 months ago
- ECDSA VHDL Implementation☆12Apr 6, 2018Updated 8 years ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 3 years ago
- Elgamal's over Elliptic Curves☆20Dec 22, 2018Updated 7 years ago
- I2C master/slave Core☆15Jul 17, 2014Updated 12 years ago
- ☆21Jan 25, 2018Updated 8 years ago
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago
- FPGA Many-core Processor Implementation☆11Nov 27, 2024Updated last year
- 64-bit multicore Linux-capable RISC-V processor☆124Apr 28, 2025Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- The OpenPiton Platform☆32May 22, 2023Updated 3 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆21Sep 2, 2023Updated 3 years ago
- PyTorch utilities to handle the KITTI Vision Benchmark Suite☆11Jul 21, 2022Updated 4 years ago
- FuseSoc Verification Automation☆22Jul 21, 2022Updated 4 years ago
- ☆21Oct 28, 2024Updated 2 years ago
- Embedded UVM (D Language port of IEEE UVM 1.0)☆35Nov 6, 2025Updated 11 months ago
- I2C slave Verilog Design and TestBench☆27May 9, 2019Updated 7 years ago
- fork from svn @ http://code.google.com/p/prettytable/☆11Oct 11, 2012Updated 14 years ago
- BSP kernel source☆12Jul 31, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Mar 5, 2019Updated 7 years ago
- APB master and slave developed in RTL.☆32Oct 25, 2025Updated last year
- Generic memory implementations☆12Feb 6, 2024Updated 2 years ago
- ☆31Feb 22, 2024Updated 2 years ago
- UM-SJTU JI VE450 2021 Summer Capstone Design Project☆10Aug 4, 2021Updated 5 years ago
- Command-line utility to return Zotero record field values given a Zotero select link, an item key, or even just a file attachment☆10Dec 23, 2023Updated 2 years ago
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆28Sep 8, 2024Updated 2 years ago
- ZCU102 two IMX274 camera design.☆12Feb 3, 2023Updated 3 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆94Jul 29, 2019Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Verilog PreProcessor.☆12Nov 9, 2015Updated 10 years ago
- ☆26Feb 15, 2025Updated last year
- Implementation of BitonicSorting algorithm on FPGA through SDAccel using Opencl as source code☆17Nov 21, 2016Updated 9 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆38Apr 9, 2026Updated 6 months ago
- Repository to hold fabscalar project and simulations☆13Mar 17, 2015Updated 11 years ago
- A mixed-signal system on chip for nanopore-based DNA sequencing☆35Nov 30, 2022Updated 3 years ago
- Build script to compile an up-to-date RISC-V GCC toolchain on Debian / Ubuntu with rv32e, rv32i and rv64i architectures and ilp32e, ilp3…☆11Jul 17, 2026Updated 3 months ago