sifive / berkeley-hardfloat-chisel3
Hardfloat using chisel3
☆17Updated 4 years ago
Alternatives and similar repositories for berkeley-hardfloat-chisel3:
Users that are interested in berkeley-hardfloat-chisel3 are comparing it to the libraries listed below
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago
- Floating point modules for CHISEL☆31Updated 10 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated last week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated last year
- Repo for all activity related to the ODSA Bunch of Wires Specification☆24Updated last year
- Useful utilities for BAR projects☆30Updated last year
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- Chisel library for Unum Type-III Posit Arithmetic☆36Updated 9 months ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- ☆15Updated 3 years ago
- ☆21Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆57Updated 2 months ago
- A vector processor implemented in Chisel☆21Updated 10 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆51Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- DASS HLS Compiler☆27Updated last year
- ☆42Updated 3 years ago
- ☆77Updated 2 years ago
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆70Updated last year
- Chisel implementation of AES☆23Updated 4 years ago
- ☆102Updated 2 years ago
- A DSL for Systolic Arrays☆78Updated 6 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆31Updated 2 months ago
- ☆77Updated 11 months ago
- Basic floating-point components for RISC-V processors☆64Updated 5 years ago
- The specification for the FIRRTL language☆51Updated this week
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated last month