freecores / reed_solomon_decoder
Reed Solomon Decoder (204,188)
☆11Updated 10 years ago
Related projects ⓘ
Alternatives and complementary repositories for reed_solomon_decoder
- DDR3 SDRAM controller☆18Updated 10 years ago
- 100 MB/s Ethernet MAC Layer Switch☆14Updated 10 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆13Updated 9 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆41Updated 6 months ago
- Python Tool for UVM Testbench Generation☆48Updated 6 months ago
- Generic AXI to AHB bridge☆15Updated 10 years ago
- Generic AXI to APB bridge☆12Updated 10 years ago
- UART -> AXI Bridge☆57Updated 3 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- SPI interface connect to APB BUS with Verilog HDL☆25Updated 3 years ago
- ☆18Updated 8 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆12Updated 2 years ago
- DMA Hardware Description with Verilog☆10Updated 4 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆42Updated 8 months ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆20Updated 7 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆44Updated 8 years ago
- ☆20Updated 5 years ago
- Implementation of the PCIe physical layer☆30Updated last week
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- This is the repository for the IEEE version of the book☆49Updated 4 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆17Updated 6 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆29Updated 6 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆21Updated 6 years ago
- AHB DMA 32 / 64 bits☆50Updated 10 years ago
- The memory model was leveraged from micron.☆19Updated 6 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆40Updated 4 years ago
- ☆16Updated 2 years ago
- ☆36Updated 3 years ago