freecores / reed_solomon_decoder
Reed Solomon Decoder (204,188)
☆11Updated 10 years ago
Alternatives and similar repositories for reed_solomon_decoder:
Users that are interested in reed_solomon_decoder are comparing it to the libraries listed below
- DDR3 SDRAM controller☆18Updated 10 years ago
- Generic AXI to AHB bridge☆16Updated 10 years ago
- ☆20Updated 5 years ago
- 100 MB/s Ethernet MAC Layer Switch☆14Updated 10 years ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- Python Tool for UVM Testbench Generation☆50Updated 8 months ago
- Generic AXI to APB bridge☆12Updated 10 years ago
- SoC Based on ARM Cortex-M3☆26Updated 2 weeks ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆41Updated 4 years ago
- Various low power labs using sky130☆11Updated 3 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆42Updated 10 months ago
- UART -> AXI Bridge☆60Updated 3 years ago
- Implementation of the PCIe physical layer☆32Updated 2 weeks ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆41Updated 8 months ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆44Updated 8 years ago
- Repository gathering basic modules for CDC purpose☆51Updated 5 years ago
- AHB DMA 32 / 64 bits☆52Updated 10 years ago
- Collection of IPs based on AMBA (AHB, APB, AXI) protocols☆19Updated 7 years ago
- This is the repository for the IEEE version of the book☆53Updated 4 years ago
- ☆18Updated 4 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆19Updated 10 months ago
- AXI4 BFM in Verilog☆31Updated 8 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆18Updated 5 years ago
- ☆16Updated 2 years ago
- UVM resource from github, run simulation use YASAsim flow☆26Updated 4 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆31Updated 2 years ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- The memory model was leveraged from micron.☆22Updated 6 years ago