freecores / reed_solomon_decoderLinks
Reed Solomon Decoder (204,188)
☆12Updated 10 years ago
Alternatives and similar repositories for reed_solomon_decoder
Users that are interested in reed_solomon_decoder are comparing it to the libraries listed below
Sorting:
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 10 years ago
- AHB DMA 32 / 64 bits☆56Updated 10 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- AXI Interconnect☆49Updated 3 years ago
- AXI4 BFM in Verilog☆32Updated 8 years ago
- Generic AXI to APB bridge☆12Updated 10 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆25Updated 8 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆56Updated last year
- ☆25Updated 4 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆21Updated 3 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆48Updated last year
- SoC Based on ARM Cortex-M3☆32Updated last month
- Generic AXI to AHB bridge☆17Updated 10 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆33Updated 2 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago
- Verification IP for APB protocol☆66Updated 4 years ago
- PCIE 5.0 Graduation project (Verification Team)☆76Updated last year
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 7 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 5 years ago
- ☆21Updated 5 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- Implementation of the PCIe physical layer☆42Updated last month
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago