freecores / reed_solomon_decoderLinks
Reed Solomon Decoder (204,188)
☆12Updated 11 years ago
Alternatives and similar repositories for reed_solomon_decoder
Users that are interested in reed_solomon_decoder are comparing it to the libraries listed below
Sorting:
- Python Tool for UVM Testbench Generation☆53Updated last year
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 11 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆60Updated last year
- Generic AXI to AHB bridge☆17Updated 11 years ago
- ☆41Updated 3 years ago
- UW reference flow for Free45PDK and The OpenROAD Project☆11Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆39Updated 2 years ago
- Verilog RTL Design☆43Updated 3 years ago
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- DDR3 SDRAM controller☆18Updated 11 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 2 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆44Updated last year
- Implementation of the PCIe physical layer☆47Updated 3 weeks ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆44Updated 3 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 5 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆68Updated 4 years ago
- round robin arbiter☆74Updated 11 years ago
- PCIE 5.0 Graduation project (Verification Team)☆78Updated last year
- AXI4 BFM in Verilog☆32Updated 8 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆61Updated last year
- UART -> AXI Bridge☆61Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆59Updated 5 years ago
- AMBA bus generator including AXI, AHB, and APB☆105Updated 4 years ago
- Ethernet 10GE MAC☆45Updated 11 years ago
- SoC Based on ARM Cortex-M3☆32Updated 2 months ago
- AXI Interconnect☆51Updated 3 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆60Updated 4 years ago