Alternatives and similar repositories for AX7103

Users that are interested in AX7103 are comparing it to the libraries listed below

• CoreyChen922 / sata_2_host_controller
  Sata 2 Host Controller for FPGA implementation
  ☆18Updated 8 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆53Updated 2 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆42Updated 4 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆84Updated 5 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆97Updated 3 years ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆27Updated 4 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆68Updated 3 years ago
• geddy11 / netwiz
  Network protocol libraries for VHDL test benches
  ☆13Updated last month
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆42Updated 4 months ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆70Updated 4 years ago
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆24Updated 5 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆97Updated 5 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆40Updated 11 months ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆48Updated 4 years ago
• siorpaes / BareBonesCortexM0
  Extremely basic CortexM0 SoC based on ARM DesignStart Eval
  ☆27Updated 7 years ago
• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆37Updated 5 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆83Updated 6 years ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆32Updated 5 years ago
• FPGANinjas / nitefury_pcie_xdma_ddr
  Interface Xilinx XDMA PCIe with DDR3 using MIG-IP on Artix-7 FPGA using Nitefury dev board
  ☆18Updated 3 years ago
• alexforencich / verilog-ft245
  Verilog FT245 to AXI stream interface
  ☆29Updated 7 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆82Updated 3 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆86Updated last year
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆34Updated 3 months ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆68Updated 5 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆44Updated last month
• ATaylorCEngFIET / Mastering-MicroBlaze
  Slides and lab instructions for the mastering MicroBlaze session
  ☆36Updated 3 years ago
• kooltzh / xilinx-coe-generator
  Python script for generating Xilinx .coe files for RAM initializing
  ☆18Updated 7 years ago
• chili-chips-ba / openPCIE
  Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes. Now for the first time in opensource…
  ☆55Updated last week
• Xilinx / revCtrl
  Revision Control Labs and Materials
  ☆25Updated 8 years ago