jlsemi / scratchipLinks
scratchip is a framework that can help to build your Chisel and Verilog/Systemverilog project easier.
☆15Updated 3 years ago
Alternatives and similar repositories for scratchip
Users that are interested in scratchip are comparing it to the libraries listed below
Sorting:
- Chisel implementation of AES☆23Updated 5 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- ☆67Updated 2 years ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.☆24Updated 2 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- ☆88Updated 2 years ago
- ☆13Updated 4 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Project repo for the POSH on-chip network generator☆52Updated 8 months ago
- Chisel components for FPGA projects☆127Updated 2 years ago
- Chisel Cheatsheet☆34Updated 2 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 2 months ago
- Wraps the NVDLA project for Chipyard integration☆22Updated 3 months ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆64Updated 2 years ago
- ☆28Updated 6 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- An open-source UCIe controller implementation☆78Updated this week
- Support for Rocket Chip on Zynq FPGAs☆40Updated 6 years ago
- ☆82Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- A dynamic verification library for Chisel.☆159Updated last year
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆33Updated 5 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆113Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆71Updated 2 weeks ago