scratchip is a framework that can help to build your Chisel and Verilog/Systemverilog project easier.
☆15Nov 2, 2022Updated 3 years ago
Alternatives and similar repositories for scratchip
Users that are interested in scratchip are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Zero Cost Abstruction of FSM(Finite State Machine) circuits based on chisel3.☆13Oct 8, 2021Updated 5 years ago
- Miscellaneous components for bluespec☆11Nov 18, 2024Updated last year
- ☆18Apr 8, 2022Updated 4 years ago
- ☆10Nov 8, 2019Updated 6 years ago
- hardware implement of huffman coding(written in verilog)☆15Jul 30, 2017Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 国自然基金Latex模板☆11Mar 12, 2023Updated 3 years ago
- ☆37Nov 11, 2018Updated 7 years ago
- Educational 16-bit MIPS Processor☆17Feb 16, 2019Updated 7 years ago
- Make Baidu EdgeBoard Lite as a general Zynq FPGA development board☆36Aug 7, 2023Updated 3 years ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- A simple SystemVerilog digital phase-locked loop based (roughly) on TI's SDLA005B application note. The design includes a SystemVerilog t…☆16Aug 29, 2022Updated 4 years ago
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- Simple benchmark to compare the performance of a various combination of asyncio event loop and zeromq implementations.☆16Dec 12, 2016Updated 9 years ago
- HDF5 Performance Analysis Checklist☆13Dec 23, 2024Updated last year
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- FFT generator using Chisel☆63Sep 26, 2021Updated 5 years ago
- Enhance CHISEL for Smooth and Comfortable Chip Design☆20Oct 6, 2026Updated last week
- Chisel implementation of AES☆24Mar 27, 2020Updated 6 years ago
- HIPP: Modern C++ Toolkit for HPC☆13Feb 24, 2023Updated 3 years ago
- AES☆16Oct 4, 2022Updated 4 years ago
- ☆23Jan 30, 2019Updated 7 years ago
- A System on a Chip Implementation for the XuLA2-LX25 board☆17Dec 13, 2018Updated 7 years ago
- Demo: how to create a custom EBRICK☆30Nov 20, 2024Updated last year
- ☆13Feb 13, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- DASS HLS Compiler☆30Oct 4, 2023Updated 3 years ago
- DMA controller for CNN accelerator☆15May 22, 2017Updated 9 years ago
- Common RTL blocks used in SiFive's projects☆194May 13, 2022Updated 4 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Jul 14, 2020Updated 6 years ago
- FT2232HL JTAG & UART Downloader☆22Jul 18, 2021Updated 5 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆13Aug 8, 2017Updated 9 years ago
- An executable specification of the RISCV ISA in L3.☆44Mar 1, 2019Updated 7 years ago
- Energy-Efficient Inference Accelerator for Memory-Augmented Neural Networks on an FPGA (DATE-19)☆15Jan 29, 2021Updated 5 years ago
- Testbenches for HDL projects☆23Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- SoftCPU/SoC engine-V☆56Apr 28, 2026Updated 5 months ago
- SciCat Data Catalogue Backend☆13Jun 15, 2023Updated 3 years ago
- Partial Verilog implimentation of a WiMAX OFDM Phy☆19May 28, 2012Updated 14 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆116Oct 31, 2023Updated 2 years ago
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 11 years ago
- ☆16Apr 21, 2019Updated 7 years ago
- AXI PSRAM Controller IP for use with Digilent Nexys 4☆11Jun 19, 2026Updated 3 months ago