gkrish19 / SIAMLinks
Scalable In-Memory Acceleration With Mesh: Device, Circuits, Architecture, and Algorithm
☆13Updated 4 years ago
Alternatives and similar repositories for SIAM
Users that are interested in SIAM are comparing it to the libraries listed below
Sorting:
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 3 years ago
- A list of our chiplet simulaters☆32Updated 2 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆53Updated last month
- A toolchain for rapid design space exploration of chiplet architectures☆50Updated last month
- ☆16Updated 3 weeks ago
- ☆32Updated this week
- An integrated CGRA design framework☆89Updated 2 months ago
- This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top…☆42Updated 2 years ago
- HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…☆36Updated 2 months ago
- ☆41Updated 11 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated 10 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆48Updated 4 years ago
- The open-sourced version of BOOM-Explorer☆40Updated 2 years ago
- ☆10Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆65Updated last month
- A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.☆21Updated 11 months ago
- Dataset for ML-guided Accelerator Design☆37Updated 6 months ago
- eyeriss-chisel3☆40Updated 3 years ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆37Updated last year
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆22Updated 3 years ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆17Updated 3 years ago
- ☆59Updated last month
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆24Updated 2 years ago
- Processing in Memory Emulation☆20Updated 2 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated 11 months ago
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆16Updated last year
- ☆26Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆53Updated 2 months ago