adamgallas / FireFly-v2Links
[TCAD'24] This repository contains the source code for the paper "FireFly v2: Advancing Hardware Support for High-Performance Spiking Neural Network with a Spatiotemporal FPGA Accelerator"
☆23Updated last year
Alternatives and similar repositories for FireFly-v2
Users that are interested in FireFly-v2 are comparing it to the libraries listed below
Sorting:
- [TVLSI'23] This repository contains the source code for the paper "FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Net…☆22Updated last year
- ☆17Updated 4 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆38Updated 6 years ago
- [FPL'24] This repository contains the source code for the paper “Revealing Untapped DSP Optimization Potentials for FPGA-based Systolic M…☆21Updated last year
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Updated 2 years ago
- Framework for radix encoded SNN on FPGA☆18Updated 4 years ago
- ☆20Updated 4 years ago
- ☆18Updated last year
- SNN on FPGA☆11Updated 3 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆63Updated 4 years ago
- SATA_Sim is an energy estimation framework for Backpropagation-Through-Time (BPTT) based Spiking Neural Networks (SNNs) training and infe…☆28Updated last year
- A repository FPGA-friendly SNN models☆35Updated 4 years ago
- Spiking Neural Network RTL Implementation☆63Updated 4 years ago
- C++ code for HLS FPGA implementation of transformer☆18Updated last year
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆16Updated 4 years ago
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆91Updated 3 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆61Updated 9 months ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆36Updated 6 years ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆21Updated last week
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆108Updated 10 months ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆74Updated 2 years ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- Open-source of MSD framework☆16Updated 2 years ago
- LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks, MICRO 2024.☆16Updated 8 months ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆41Updated 2 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆25Updated last year
- A nest brain simulator based on FPGA(LIF NEURON)☆14Updated 3 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆19Updated 6 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆139Updated 9 months ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆25Updated 5 years ago