Alternatives and similar repositories for supervisor-mips32

Users that are interested in supervisor-mips32 are comparing it to the libraries listed below

• thu-cs-lab / thinpad_top

  View on GitHub
  Project template for Artix-7 based Thinpad board
  ☆52Sep 13, 2025Updated 5 months ago
• MashPlant / re2dfa

  View on GitHub
  Convert regex(es) to dfa.
  ☆14Apr 30, 2021Updated 4 years ago
• thu-cs-lab / Router-Lab

  View on GitHub
  Lab for Network Principles since 2019-2020 fall
  ☆175Sep 22, 2025Updated 4 months ago
• Harry-Chen / HERMES

  View on GitHub
  HERMES: sHallow dirEctory stRucture Many-filE fileSystem
  ☆20Jun 9, 2019Updated 6 years ago
• jiegec / naiverouter

  View on GitHub
  A router IP written in Verilog.
  ☆12Dec 20, 2019Updated 6 years ago
• jiegec / learn_tsinghua_app

  View on GitHub
  网络学堂 PC 端 App
  ☆21Feb 4, 2023Updated 3 years ago
• oscourse-tsinghua / cpu-testcase

  View on GitHub
  Test cases for MIPS CPU implementation
  ☆12Dec 26, 2019Updated 6 years ago
• meow-chip / MeowRouter

  View on GitHub
  A hardware accelerated IP packet forwarder running on programmable ICs
  ☆15Jan 21, 2023Updated 3 years ago
• thu-cs-lab / JieLabs-Web

  View on GitHub
  Backend & Frontend for JieLabs
  ☆22Mar 3, 2023Updated 2 years ago
• z4yx / NaiveMIPS-HDL

  View on GitHub
  Naïve MIPS32 SoC implementation
  ☆118Jun 23, 2020Updated 5 years ago
• cnyangkun / nscscc2018

  View on GitHub
  nscscc2018
  ☆27Oct 11, 2018Updated 7 years ago
• trivialmips / TrivialMIPS

  View on GitHub
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆109Apr 29, 2019Updated 6 years ago
• LyricZhao / THU-Bell

  View on GitHub
  THU Bell on macOS
  ☆28Feb 24, 2020Updated 5 years ago
• jiegec / jtag-remote-server

  View on GitHub
  Remote JTAG server for remote debugging
  ☆43Dec 31, 2025Updated last month
• z4yx / ucore-thumips

  View on GitHub
  uCore MIPS32 porting
  ☆18Dec 16, 2019Updated 6 years ago
• cyyself / CDIM-SoC

  View on GitHub
  SoC for CQU Dual Issue Machine
  ☆12Sep 20, 2022Updated 3 years ago
• thu-cs-lab / supervisor-rv

  View on GitHub
  计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位
  ☆127Dec 4, 2025Updated 2 months ago
• meow-chip / MeowV64

  View on GitHub
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Feb 17, 2022Updated 3 years ago
• MashPlant / lalr1

  View on GitHub
  An LALR1(1)/LL(1) parser generator in Rust, for multiple languages.
  ☆49Mar 29, 2022Updated 3 years ago
• decaf-lang / decaf

  View on GitHub
  The new Decaf compiler, rewritten in "modern" Java
  ☆66Jul 21, 2020Updated 5 years ago
• decaf-lang / decaf-rs

  View on GitHub
  The Decaf compiler, written in Rust
  ☆57Dec 18, 2019Updated 6 years ago
• dramforever / urvirt

  View on GitHub
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆14Feb 11, 2022Updated 4 years ago
• xyongcn / LoongsonCsprj2017

  View on GitHub
  Computer System Project for Loongson FPGA Board in 2017
  ☆54Jun 3, 2018Updated 7 years ago
• oscomp / proj23-lightweight-hypervisor

  View on GitHub
  在RISC-V处理器上实现一个轻量级的Hypervisor。
  ☆12Dec 25, 2020Updated 5 years ago
• CircuitCoder / MeowRust

  View on GitHub
  Relaxed Rust (for cats)
  ☆14Nov 20, 2019Updated 6 years ago
• Harry-Chen / thu-learn-lib

  View on GitHub
  A JavaScript library to provide a program-friendly interface to Web Learning of Tsinghua University
  ☆77Feb 5, 2026Updated last week
• typekernel / typekernel

  View on GitHub
  Warning: 🕳 ahead!
  ☆16Jan 8, 2020Updated 6 years ago
• oscourse-tsinghua / LoongsonCsprj2017-manual

  View on GitHub
  基于龙芯FPGA开发板的计算机综合系统实验
  ☆26Dec 16, 2018Updated 7 years ago
• CircuitCoder / mill

  View on GitHub
  RV32I by cats
  ☆15Sep 4, 2023Updated 2 years ago
• efeslab / eecs582

  View on GitHub
  Course website for Advanced Operating Systems
  ☆13Apr 8, 2022Updated 3 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020

  View on GitHub
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆50Dec 11, 2023Updated 2 years ago
• rcore-os / rCore_tutorial

  View on GitHub
  Tutorial for rCore OS step by step (2nd edition)
  ☆141Dec 4, 2022Updated 3 years ago
• z4yx / vivado-docker

  View on GitHub
  Dockerfile with Vivado for CI
  ☆27Apr 17, 2020Updated 5 years ago
• jiegec / verilog-format

  View on GitHub
  A naive verilog/systemverilog formatter
  ☆21Mar 22, 2025Updated 10 months ago
• cyyself / cyyrv64

  View on GitHub
  My RV64 CPU (Work in progress)
  ☆19Dec 22, 2022Updated 3 years ago
• shanghai-edu / radius-1xtest

  View on GitHub
  ☆12Jul 3, 2018Updated 7 years ago
• jiegec / Projects

  View on GitHub
  A summary of my projects
  ☆49Dec 29, 2025Updated last month
• xalanq / jarvisoj-solutions

  View on GitHub
  CTF - Jarvis OJ 我的题解
  ☆36Aug 11, 2019Updated 6 years ago
• SocialistDalao / UltraMIPS_NSCSCC

  View on GitHub
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆147Jun 23, 2024Updated last year