vsdip / avsddac_3v3_sky130_v2Links
☆16Updated 2 years ago
Alternatives and similar repositories for avsddac_3v3_sky130_v2
Users that are interested in avsddac_3v3_sky130_v2 are comparing it to the libraries listed below
Sorting:
- ☆12Updated 3 years ago
- ☆41Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆70Updated 4 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆23Updated 6 years ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆17Updated last month
- repository for a bandgap voltage reference in SKY130 technology☆38Updated 2 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆43Updated 3 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆33Updated 3 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆12Updated 4 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆70Updated 4 years ago
- SRAM☆22Updated 4 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆45Updated 3 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- Open source process design kit for 28nm open process☆59Updated last year
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆27Updated 2 years ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆14Updated 6 years ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆63Updated last month
- submission repository for efabless mpw6 shuttle☆30Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- ☆12Updated 11 months ago
- ☆20Updated 3 years ago
- PLL Designs on Skywater 130nm MPW☆20Updated last year
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- A 10bit SAR ADC in Sky130☆25Updated 2 years ago
- This repository contains all the information studied and created during the [Advanced Physical Design Using OpenLANE / SKY130](https://ww…☆17Updated 2 years ago
- cdsAsync: An Asynchronous QDI VLSI Toolset & Schematic Library☆25Updated 5 years ago