Base on Synopsys platform using VCS,DC,ICC,PT.
☆11May 29, 2021Updated 4 years ago
Alternatives and similar repositories for ASIC-design-example-RISC-CPU
Users that are interested in ASIC-design-example-RISC-CPU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Syno…☆14Jun 9, 2021Updated 4 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Apr 15, 2021Updated 5 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆16Aug 18, 2022Updated 3 years ago
- ECE 5745 Tutorial 8: SRAM Generators☆14Mar 5, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- 从零开始学 AI Agent 开发 | 系统、全面、实战导向的 Agent 开发教程 | 每日自动追踪 arXiv 最新论文 | Learn AI Agent Development from Scratch☆115Updated this week
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆39Jun 2, 2021Updated 4 years ago
- Pipelined RISC-V CPU☆27Jun 9, 2021Updated 4 years ago
- EE 287 2012 Fall☆33Mar 11, 2013Updated 13 years ago
- Bugs Everywhere (BE), a bugtracker built on distributed version control.☆16Nov 17, 2016Updated 9 years ago
- Example of a full DC synthesis script for a simple design☆14Feb 25, 2019Updated 7 years ago
- Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment☆15Sep 17, 2019Updated 6 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆43Jun 3, 2020Updated 5 years ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆13Sep 28, 2022Updated 3 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- AVR CPU Core Implementation in Verilog HDL.☆15Oct 28, 2018Updated 7 years ago
- Converting Boolean expressions to CMOS Circuits☆11Oct 6, 2020Updated 5 years ago
- Black Duck Detect plugin for Jenkins☆12Apr 9, 2026Updated 2 weeks ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- Interface Xilinx XDMA PCIe with DDR3 using MIG-IP on Artix-7 FPGA using Nitefury dev board☆18Apr 13, 2022Updated 4 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆11Oct 3, 2017Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- O'Reilly Course, In-Memory Computing Essentials☆10Oct 16, 2020Updated 5 years ago
- The development tree for OpenOCD for the Synopsys DesignWare ARC processor family☆16Mar 23, 2026Updated last month
- UVM Python Verification Agents Library☆15Mar 18, 2021Updated 5 years ago
- Fixed Point Kalman filter for fpga☆25May 10, 2020Updated 5 years ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 4 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆15Dec 1, 2023Updated 2 years ago
- A CircuitPython driver class for the NAU7802 24-bit ADC☆13Mar 30, 2026Updated 3 weeks ago
- This place provide different SRAM cells netlist to be simulated with HSpice tool in sub-20nm FinFET technologies.☆12Dec 31, 2020Updated 5 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Lecture Material on Deep Learning Inference using FPGA☆12Jun 9, 2020Updated 5 years ago
- Design of BandGapReference Circuit using Sky130 PDK☆11Oct 30, 2021Updated 4 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆16Apr 17, 2021Updated 5 years ago
- ☆10Dec 15, 2023Updated 2 years ago
- AMC: Asynchronous Memory Compiler☆53Jun 29, 2020Updated 5 years ago
- Replaces the 16 DRAM chips with a small module of SRAM☆11Feb 16, 2021Updated 5 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆14Jul 31, 2024Updated last year