ehao222 / ASIC-design-example-RISC-CPULinks
Base on Synopsys platform using VCS,DC,ICC,PT.
☆12Updated 4 years ago
Alternatives and similar repositories for ASIC-design-example-RISC-CPU
Users that are interested in ASIC-design-example-RISC-CPU are comparing it to the libraries listed below
Sorting:
- ☆34Updated 6 years ago
- General Purpose AXI Direct Memory Access☆51Updated last year
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆20Updated 2 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆33Updated 2 years ago
- ☆55Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆33Updated 5 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆16Updated 3 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆12Updated 2 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆19Updated last year
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆12Updated 2 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆22Updated 4 months ago
- ☆29Updated 4 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆56Updated last year
- Asynchronous fifo in verilog☆35Updated 9 years ago
- AXI Interconnect☆49Updated 3 years ago
- ☆25Updated 4 years ago
- SoC Based on ARM Cortex-M3☆32Updated last month
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- CORE-V MCU UVM Environment and Test Bench☆21Updated 11 months ago
- ☆27Updated 5 years ago
- DOULOS Easier UVM Code Generator☆34Updated 8 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 4 years ago
- UVM resource from github, run simulation use YASAsim flow☆27Updated 5 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago