mattvenn / fpga-fft
☆13Updated 4 years ago
Alternatives and similar repositories for fpga-fft:
Users that are interested in fpga-fft are comparing it to the libraries listed below
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- ☆33Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆25Updated 3 years ago
- ☆59Updated 3 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆34Updated 6 years ago
- Time to Digital Converter (TDC)☆30Updated 4 years ago
- Reconfigurable Binary Engine☆15Updated 3 years ago
- Open Source AES☆31Updated 10 months ago
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆16Updated last year
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆28Updated 3 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆19Updated this week
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆21Updated 11 months ago
- MMC (and derivative standards) host controller☆23Updated 4 years ago
- ULPI Link Wrapper (USB Phy Interface)☆25Updated 4 years ago
- SAR ADC on tiny tapeout☆39Updated last month
- ☆27Updated 4 years ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆4Updated 2 years ago
- FPGA board-level debugging and reverse-engineering tool☆34Updated last year
- 基于Kintex-7 XC7K325T的高性能FPGA功能验证板☆19Updated 5 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 2 months ago
- DSP WishBone Compatible Cores☆13Updated 10 years ago
- Fixed-point math library with VHDL, Python and MATLAB support☆20Updated last week
- A simple, scalable, source-synchronous, all-digital DDR link☆22Updated 3 weeks ago
- A Mel-frequency cepstrum core in FPGA☆17Updated 3 years ago
- USB -> AXI Debug Bridge☆36Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆30Updated this week
- Open-Source HLS Examples for Microchip FPGAs☆42Updated 2 months ago
- ☆37Updated 3 years ago