mattvenn / fpga-fftLinks
☆13Updated 5 years ago
Alternatives and similar repositories for fpga-fft
Users that are interested in fpga-fft are comparing it to the libraries listed below
Sorting:
- Network protocol libraries for VHDL test benches☆12Updated 3 months ago
- Fixed-point math library with VHDL, Python and MATLAB support☆27Updated 2 weeks ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆37Updated 6 years ago
- Repository containing the DSP gateware cores☆13Updated last month
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆18Updated 4 months ago
- ☆33Updated 2 years ago
- Triple Modular Redundancy☆27Updated 5 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆19Updated last month
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆19Updated 2 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- VHDL PCIe Transceiver☆29Updated 5 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 4 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Updated 2 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆20Updated 6 months ago
- Approximate arithmetic circuits for FPGAs☆12Updated 5 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- SAR ADC on tiny tapeout☆42Updated 6 months ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆46Updated last year
- SDRAM controller for MIPSfpga+ system☆23Updated 4 years ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆23Updated last year
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆28Updated last year
- Reusable image processing modules in SystemVerilog☆34Updated 8 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- PNG encoder, implemented in VHDL☆23Updated last year
- A current mode buck converter on the SKY130 PDK☆28Updated 4 years ago
- ☆14Updated 4 months ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago