ecelab-org / Split-Chip_authenticationLinks
An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.
☆17Updated 5 years ago
Alternatives and similar repositories for Split-Chip_authentication
Users that are interested in Split-Chip_authentication are comparing it to the libraries listed below
Sorting:
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 5 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆19Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆40Updated 5 years ago
- FPGA implementation of a physical unclonable function for authentication☆33Updated 8 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆30Updated 3 months ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆23Updated 7 years ago
- Asynchronous FIFO for transferring data between two asynchronous clock domains☆18Updated 9 years ago
- few python scripts to clone all IP cores from opencores.org☆24Updated last year
- General Purpose AXI Direct Memory Access☆59Updated last year
- A simple implementation of the Karatsuba multiplication algorithm☆11Updated 6 months ago
- Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…☆49Updated 10 years ago
- Elgamal's over Elliptic Curves☆19Updated 6 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆31Updated 3 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 7 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆47Updated 3 years ago
- True Random Number Generator core implemented in Verilog.☆76Updated 5 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- ☆13Updated 10 years ago
- RISC-V instruction set extensions for SM4 block cipher☆20Updated 5 years ago
- A simple DDR3 memory controller☆60Updated 2 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆66Updated 8 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- ☆20Updated 2 years ago
- Advanced encryption standard implementation in verilog.☆31Updated 3 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- Ring Oscillator Physically Unclonable Funtion☆25Updated 4 years ago