ecelab-org / Split-Chip_authenticationLinks
An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.
☆17Updated 6 years ago
Alternatives and similar repositories for Split-Chip_authentication
Users that are interested in Split-Chip_authentication are comparing it to the libraries listed below
Sorting:
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆13Updated 6 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆19Updated 6 years ago
- Repository to store all design and testbench files for Senior Design☆22Updated 5 years ago
- ☆21Updated 2 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆42Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆24Updated 8 years ago
- Ring Oscillator Physically Unclonable Funtion☆26Updated 4 years ago
- few python scripts to clone all IP cores from opencores.org☆26Updated 2 years ago
- FPGA implementation of a physical unclonable function for authentication☆33Updated 8 years ago
- Asynchronous FIFO for transferring data between two asynchronous clock domains☆17Updated 9 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆34Updated last month
- System Verilog and Emulation. Written all the five channels.☆35Updated 8 years ago
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆32Updated 7 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Updated 4 years ago
- An FPGA Implementation of Arbiter PUF with 4x4 Switch Blocks☆16Updated 5 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Updated this week
- RISC-V instruction set extensions for SM4 block cipher☆21Updated 5 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆54Updated 4 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆100Updated 7 months ago
- USB -> AXI Debug Bridge☆42Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆61Updated 5 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆56Updated 7 years ago
- Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…☆53Updated 10 years ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆22Updated 8 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆27Updated 2 months ago
- ☆13Updated 10 years ago
- ☆33Updated 2 months ago