ecelab-org / Split-Chip_authentication
An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.
☆15Updated 4 years ago
Related projects: ⓘ
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 4 years ago
- ☆12Updated 9 years ago
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆20Updated 6 years ago
- RISC-V instruction set extensions for SM4 block cipher☆18Updated 4 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆16Updated 5 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆13Updated last year
- Verilog based FPGA Design of SHA256 Simulated on ModelSim☆19Updated 6 years ago
- Repository to store all design and testbench files for Senior Design☆17Updated 4 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆35Updated 4 years ago
- RISC-V soft-core PEs for TaPaSCo☆15Updated 3 months ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆21Updated 2 years ago
- Asynchronous FIFO for transferring data between two asynchronous clock domains☆16Updated 8 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆29Updated 3 years ago
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Updated 3 years ago
- Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…☆39Updated 9 years ago
- Custom Coprocessor Interface for VexRiscv☆10Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆39Updated 3 years ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆4Updated last year
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆43Updated 2 years ago
- Open FPGA Modules☆22Updated last week
- FPGA implementation of Chinese SM4 encryption algorithm.☆44Updated 6 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆18Updated last month
- Elgamal's over Elliptic Curves☆16Updated 5 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆25Updated 6 months ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆24Updated 3 years ago
- Verilog Implementation of modular exponentiation using Montgomery multiplication☆32Updated 9 years ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆21Updated 3 months ago
- The Verilog source code for DRUM approximate multiplier.☆26Updated last year
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆11Updated 7 months ago