Alternatives and similar repositories for general-cores

Users that are interested in general-cores are comparing it to the libraries listed below

• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆49Updated last month
• opalkelly-opensource / design-resources
  A collection of Opal Kelly provided design resources
  ☆17Updated last week
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆28Updated last month
• lewiz-support / LMAC_CORE1
  LMAC Core1 - Ethernet 1G/100M/10M
  ☆18Updated 2 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆35Updated 8 months ago
• hVHDL / hVHDL_floating_point
  high level VHDL floating point library for synthesis in fpga
  ☆18Updated this week
• lnls-dig / dsp-cores
  Repository containing the DSP gateware cores
  ☆14Updated 2 weeks ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆31Updated 3 years ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆66Updated this week
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• Cognoscan / BoostDSP
  VHDL Library for implementing common DSP functionality.
  ☆30Updated 7 years ago
• ThalesGroup / TMR
  Triple Modular Redundancy
  ☆27Updated 6 years ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆31Updated 5 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆62Updated this week
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆43Updated 6 years ago
• ultraembedded / core_mmc
  MMC (and derivative standards) host controller
  ☆24Updated 5 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆95Updated 5 years ago
• tgingold / OpenTDC
  Time to Digital Converter (TDC)
  ☆34Updated 4 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆52Updated 2 years ago
• paulscherrerinstitute / PsiIpPackage
  TCL framework to package Vivado IP-Cores
  ☆14Updated 3 years ago
• alexforencich / verilog-ft245
  Verilog FT245 to AXI stream interface
  ☆29Updated 7 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• noasic / noasic
  An open-source VHDL library for FPGA design.
  ☆32Updated 3 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated last month
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆18Updated 13 years ago
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆25Updated 4 months ago
• subutai-attic / pars
  ☆30Updated 8 years ago