general-cores
☆21Jul 16, 2025Updated last year
Alternatives and similar repositories for general-cores
Users that are interested in general-cores are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 6 months ago
- LiteX based White Rabbit PCIe NIC developped for Warsaw University of Technology.☆27Updated this week
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 8 years ago
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- DSPIRA telescope hardware designs, schematics, board layouts, and fabrication files.☆12Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Example of Test Driven Design with VUnit☆16Nov 22, 2021Updated 4 years ago
- ChimeraTK core library: Provide (client) access to hardware devices and other control system applications.☆12Updated this week
- SystemVerilog Logger☆19Apr 6, 2026Updated 5 months ago
- Library with VHDL cores implementing Advanced Microcontroller Bus Architecture 5 (AMBA5) specifications such as APB, AHB, AXI, and AXI-St…☆18Sep 6, 2026Updated 3 weeks ago
- An open-source HDL register code generator fast enough to run in real time.☆91Updated this week
- Revision Control Labs and Materials☆26Jan 23, 2018Updated 8 years ago
- Open source firmware for MMC controllers☆46May 28, 2025Updated last year
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 10 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- RISC-V soft-core PEs for TaPaSCo☆24Jul 24, 2026Updated 2 months ago
- A standalone parser for BSV (Bluespec SystemVerilog) written in Go☆14Dec 20, 2016Updated 9 years ago
- Hardware and script files related to dynamic partial reconfiguration☆11Mar 16, 2018Updated 8 years ago
- cryptography ip-cores in vhdl / verilog☆42Feb 20, 2021Updated 5 years ago
- A Bluespec SystemVerilog library of miscellaneous components☆18Jul 10, 2026Updated 2 months ago
- SCons (make-like) scripts for building FPGA code with Xilinx tools☆18Jul 16, 2012Updated 14 years ago
- A collection of Opal Kelly provided design resources☆19Jun 15, 2026Updated 3 months ago
- Control and status register code generator toolchain☆212Sep 1, 2026Updated 3 weeks ago
- Library for reading Xilinx .bit bitstream file headers with metadata extraction☆14Apr 7, 2026Updated 5 months ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- VHDL Library for implementing common DSP functionality.☆33Oct 5, 2018Updated 7 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆70Feb 16, 2026Updated 7 months ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆17Jul 17, 2016Updated 10 years ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆219Updated this week
- VHDL related news.☆27Updated this week
- Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)☆11Dec 16, 2019Updated 6 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- Wishbone to AXI bridge (VHDL)☆51Aug 29, 2019Updated 7 years ago
- TCL framework to package Vivado IP-Cores☆13May 18, 2022Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆21Jul 4, 2026Updated 2 months ago
- High performance embedded systems for stereoscopic vision☆11Jul 23, 2019Updated 7 years ago
- A library of verilog and vhdl modules☆15Nov 13, 2018Updated 7 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆36Jul 10, 2016Updated 10 years ago
- This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from C…☆21Jul 28, 2025Updated last year
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Jun 29, 2019Updated 7 years ago
- FPGA Development toolset☆20Jun 15, 2017Updated 9 years ago