lnls-dig / general-coresLinks
general-cores
☆21Updated 2 months ago
Alternatives and similar repositories for general-cores
Users that are interested in general-cores are comparing it to the libraries listed below
Sorting:
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆64Updated last week
- Extensible FPGA control platform☆62Updated 2 years ago
- VHDL PCIe Transceiver☆30Updated 5 years ago
- Library of reusable VHDL components☆28Updated last year
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- This repository contains synthesizable examples which use the PoC-Library.☆38Updated 4 years ago
- LMAC Core1 - Ethernet 1G/100M/10M☆18Updated 2 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆33Updated 8 years ago
- ☆33Updated 2 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆66Updated last week
- Small footprint and configurable JESD204B core☆44Updated 3 months ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆34Updated 6 months ago
- ☆20Updated 3 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated 2 years ago
- Generic Logic Interfacing Project☆47Updated 5 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆47Updated 10 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- An open-source VHDL library for FPGA design.☆31Updated 3 years ago
- Wishbone to AXI bridge (VHDL)☆42Updated 6 years ago
- USB Full Speed PHY☆45Updated 5 years ago
- Triple Modular Redundancy☆27Updated 6 years ago
- Fixed-point math library with VHDL, Python and MATLAB support☆27Updated last month
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Updated 7 years ago
- SERDES-based TDC core for Spartan-6☆18Updated 13 years ago
- Repository containing the DSP gateware cores☆13Updated last week
- Verilog Repository for GIT☆33Updated 4 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- ☆30Updated 8 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆94Updated 5 years ago