lnls-dig / general-cores
general-cores
☆19Updated 7 months ago
Alternatives and similar repositories for general-cores
Users that are interested in general-cores are comparing it to the libraries listed below
Sorting:
- Library of reusable VHDL components☆28Updated last year
- ☆20Updated 2 years ago
- Extensible FPGA control platform☆60Updated 2 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- Repository containing the DSP gateware cores☆13Updated 7 months ago
- Harmon Instruments FIFO to PCI Express interface☆11Updated 4 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- Fixed-point math library with VHDL, Python and MATLAB support☆22Updated 2 months ago
- VHDL PCIe Transceiver☆28Updated 4 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆23Updated 5 months ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆33Updated 7 years ago
- FPGA board-level debugging and reverse-engineering tool☆37Updated 2 years ago
- TCL framework to package Vivado IP-Cores☆15Updated 2 years ago
- Small footprint and configurable JESD204B core☆42Updated 3 weeks ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆27Updated 4 months ago
- SERDES-based TDC core for Spartan-6☆18Updated 12 years ago
- cryptography ip-cores in vhdl / verilog☆40Updated 4 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- This repository contains synthesizable examples which use the PoC-Library.☆37Updated 4 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- VHDL Library for implementing common DSP functionality.☆27Updated 6 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Revision Control Labs and Materials☆24Updated 7 years ago
- Verilog Repository for GIT☆32Updated 4 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆44Updated 9 years ago
- A collection of Opal Kelly provided design resources☆16Updated 2 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆32Updated last week
- IP Cores that can be used within Vivado☆25Updated 3 years ago
- Example of Test Driven Design with VUnit☆14Updated 3 years ago
- ☆26Updated last year