rgwan / AMBALinks
Collection of IPs based on AMBA (AHB, APB, AXI) protocols
☆20Updated 8 years ago
Alternatives and similar repositories for AMBA
Users that are interested in AMBA are comparing it to the libraries listed below
Sorting:
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- ☆20Updated 2 years ago
- ☆21Updated 5 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆46Updated 9 years ago
- Implementation of the PCIe physical layer☆50Updated 3 months ago
- ☆24Updated 3 months ago
- ☆21Updated 6 years ago
- soc integration script and integration smoke script☆23Updated 3 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 7 years ago
- Generate UVM testbench framework template files with Python 3☆26Updated 5 years ago
- Verification IP for UART protocol☆20Updated 5 years ago
- ☆26Updated 4 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆27Updated 8 months ago
- General Purpose AXI Direct Memory Access☆60Updated last year
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 11 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- Verification IP for APB protocol☆70Updated 4 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆16Updated 2 years ago
- This is the repository for the IEEE version of the book☆74Updated 5 years ago
- AXI Interconnect☆53Updated 4 years ago
- AXI4 with a FIFO integrated with VIP☆22Updated last year
- Asynchronous fifo in verilog☆35Updated 9 years ago
- UVM Testbench For SystemVerilog Combinator Implementation☆56Updated 8 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆43Updated 5 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 7 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆13Updated 5 years ago