rgwan / AMBALinks
Collection of IPs based on AMBA (AHB, APB, AXI) protocols
☆20Updated 8 years ago
Alternatives and similar repositories for AMBA
Users that are interested in AMBA are comparing it to the libraries listed below
Sorting:
- ☆21Updated 5 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- ☆20Updated 3 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆46Updated 9 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆25Updated 6 years ago
- soc integration script and integration smoke script☆24Updated 3 years ago
- Implementation of the PCIe physical layer☆60Updated 6 months ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆19Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Updated 11 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- ☆26Updated 4 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- System Verilog and Emulation. Written all the five channels.☆35Updated 8 years ago
- Verification IP for AMBA APB Protocol☆33Updated 2 years ago
- AXI Interconnect☆54Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆61Updated 5 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- Verification IP for UART protocol☆22Updated 5 years ago
- UVM Testbench for synchronus fifo☆19Updated 5 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 7 years ago
- SoC Based on ARM Cortex-M3☆36Updated 7 months ago
- Repository gathering basic modules for CDC purpose☆57Updated 6 years ago
- UART -> AXI Bridge☆69Updated 4 years ago
- ☆28Updated 6 months ago
- Implements a simple UVM based testbench for a simple memory DUT.☆13Updated 6 years ago
- ☆22Updated 6 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆37Updated 3 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆31Updated 11 months ago
- uvm_axi is a uvm package for modeling and verifying AXI protocol☆20Updated 11 months ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 6 years ago