Collection of IPs based on AMBA (AHB, APB, AXI) protocols
☆19Feb 1, 2017Updated 9 years ago
Alternatives and similar repositories for AMBA
Users that are interested in AMBA are comparing it to the libraries listed below
Sorting:
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Jul 29, 2014Updated 11 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆31Jan 6, 2020Updated 6 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆159Mar 31, 2020Updated 5 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆17Mar 15, 2018Updated 8 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆13Oct 26, 2019Updated 6 years ago
- System Verilog and Emulation. Written all the five channels.☆35Mar 9, 2017Updated 9 years ago
- To design test bench of the APB protocol☆18Dec 30, 2020Updated 5 years ago
- Code snippets from articles published on www.amiq.com/consulting/blog☆37Jun 14, 2024Updated last year
- ☆10Aug 12, 2021Updated 4 years ago
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 3 years ago
- AES☆15Oct 4, 2022Updated 3 years ago
- RISC-V soft-core PEs for TaPaSCo☆23Jan 30, 2026Updated last month
- A Tcl-Library for scripted HDL generation☆17Apr 30, 2024Updated last year
- This repository contains the design and simulation process and results of potentiometric digital to analog converter.☆15Oct 6, 2020Updated 5 years ago
- Verilog Repository for GIT☆35May 4, 2021Updated 4 years ago
- Memory Level Verification of Dual Port RAM using SystemVerilog and Universal Verification Methodology Environments with assertions,functi…☆30Nov 21, 2020Updated 5 years ago
- DMA controller for CNN accelerator☆14May 22, 2017Updated 8 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆193Jul 23, 2018Updated 7 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆48May 10, 2024Updated last year
- Testbenches for HDL projects☆22Updated this week
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- A complete UVM verification testbench for FIFO☆13Mar 21, 2016Updated 10 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 8 years ago
- AHB3-Lite Interconnect☆109May 10, 2024Updated last year
- ☆10Sep 7, 2023Updated 2 years ago
- amba3 apb/axi vip☆52Feb 24, 2015Updated 11 years ago
- Ten Thousand Failures Blog☆12Jul 22, 2014Updated 11 years ago
- ☆10Nov 8, 2019Updated 6 years ago
- ☆16Apr 21, 2019Updated 6 years ago
- ☆18May 5, 2022Updated 3 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- AMBA bus lecture material☆516Jan 21, 2020Updated 6 years ago
- Reed Solomon Decoder (204,188)☆13Jul 17, 2014Updated 11 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆23Jul 6, 2018Updated 7 years ago
- UVM APB VIP, part of AMBA3&AMBA4 feature supported☆34Aug 24, 2020Updated 5 years ago