vladniculescu / High-Speed-FPGA-based-Data-Acquisition-System-100MSPSLinks
☆19Updated 2 years ago
Alternatives and similar repositories for High-Speed-FPGA-based-Data-Acquisition-System-100MSPS
Users that are interested in High-Speed-FPGA-based-Data-Acquisition-System-100MSPS are comparing it to the libraries listed below
Sorting:
- Testbenches for HDL projects☆22Updated this week
- Interface Protocol in Verilog☆50Updated 6 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆16Updated 11 months ago
- Groundhog - Serial ATA Host Bus Adapter☆24Updated 7 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆67Updated last week
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- FIR band-pass filter using Verilog HDL.☆12Updated 5 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆31Updated 4 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆22Updated 7 years ago
- SPI Master Core clone from OpenCores☆11Updated 12 years ago
- IP operations in verilog (simulation and implementation on ice40)☆61Updated 6 years ago
- USB -> AXI Debug Bridge☆40Updated 4 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆59Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- SPI-Flash XIP Interface (Verilog)☆46Updated 4 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆10Updated 5 years ago
- Project in Course named DESIGN AND IMPLEMENTATION OF COMMUNICATION PROTOCOLS in FCU☆14Updated 11 years ago
- A collection of phase locked loop (PLL) related projects☆112Updated last year
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆61Updated 3 years ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆67Updated 4 years ago
- ☆19Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- TCL scripts for FPGA (Xilinx)☆34Updated 3 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆30Updated 2 years ago
- Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).☆61Updated 3 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated last week
- ☆26Updated 4 months ago