vladniculescu / High-Speed-FPGA-based-Data-Acquisition-System-100MSPSLinks
☆19Updated last year
Alternatives and similar repositories for High-Speed-FPGA-based-Data-Acquisition-System-100MSPS
Users that are interested in High-Speed-FPGA-based-Data-Acquisition-System-100MSPS are comparing it to the libraries listed below
Sorting:
- development interface mil-std-1553b for system on chip☆22Updated 7 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- Testbenches for HDL projects☆19Updated this week
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆61Updated 3 years ago
- ☆17Updated 3 weeks ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 3 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆16Updated 8 months ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- Groundhog - Serial ATA Host Bus Adapter☆23Updated 7 years ago
- SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs☆17Updated 5 years ago
- JESD204B core for Migen/MiSoC☆36Updated 4 years ago
- A collection of Opal Kelly provided design resources☆17Updated 4 months ago
- minimal code to access ps DDR from PL☆20Updated 5 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆30Updated 4 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆53Updated 2 years ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆65Updated 3 years ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆32Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA☆18Updated last year
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- Open FPGA Modules☆24Updated 10 months ago
- ☆19Updated 4 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- FIR band-pass filter using Verilog HDL.☆12Updated 4 years ago
- Gaussian noise generator Verilog IP core☆31Updated 2 years ago
- SERDES-based TDC core for Spartan-6☆18Updated 13 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- A collection of phase locked loop (PLL) related projects☆107Updated last year