Alternatives and similar repositories for High-Speed-FPGA-based-Data-Acquisition-System-100MSPS

Users that are interested in High-Speed-FPGA-based-Data-Acquisition-System-100MSPS are comparing it to the libraries listed below

• analogdevicesinc / testbenches
  Testbenches for HDL projects
  ☆22Updated this week
• xycfwrj / zynq_axi_ddr_barebone
  minimal code to access ps DDR from PL
  ☆21Updated 6 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆112Updated last year
• hkhajanchi / fpga-pid
  Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA
  ☆32Updated 5 years ago
• madamic / zynq_tdc
  A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC
  ☆68Updated 4 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• fpga-soc / mil-std-1553b-soc
  development interface mil-std-1553b for system on chip
  ☆23Updated 7 years ago
• uestcXJW / FIR_Filter
  A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB
  ☆10Updated 5 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆71Updated last month
• uwemeyerbaese / DSP_with_FPGAs_ed3
  DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8
  ☆15Updated last month
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆60Updated 3 years ago
• ericgineer / CIC
  A CIC filter implemented in Verilog
  ☆24Updated 10 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• liuguangxi / gng
  Gaussian noise generator Verilog IP core
  ☆32Updated 2 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆93Updated 3 years ago
• xfguo / spi
  SPI Master Core clone from OpenCores
  ☆11Updated 12 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• patocarr / axi-traffic-gen
  File editor for the Xilinx AXI Traffic Generator IP
  ☆16Updated last year
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 6 years ago
• filipamator / adpll
  All digital PLL
  ☆28Updated 7 years ago
• JoseIuri / axi4lite2uart
  This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.
  ☆22Updated 7 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆80Updated 3 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆32Updated 9 years ago
• Wissance / QuickSPI
  Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
  ☆21Updated 8 years ago
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆18Updated 13 years ago
• manjushpv / Design-and-Verification-of-Nand-Flash-Memory-Controller
  - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash).
 - Implemented operations : …
  ☆21Updated 7 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆52Updated 2 years ago
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆38Updated 10 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆61Updated 6 years ago