Alternatives and similar repositories for Digilent-Maker:

Users that are interested in Digilent-Maker are comparing it to the libraries listed below

• DigilentInc / vivado-library
  ☆35Updated 6 years ago
• swetland / zynq-sandbox
  a playground for xilinx zynq fpga experiments
  ☆48Updated 6 years ago
• andrewandrepowell / VGA_1.0
  AXI memory-mapped VGA module originally designed for the Avent Zedboard
  ☆15Updated 8 years ago
• jpiat / hard-cv
  A repository of IPs for hardware computer vision (FPGA)
  ☆95Updated 9 years ago
• RISCV-on-Microsemi-FPGA / SoftConsole
  Eclipse based IDE for RISC-V bare metal software development.
  ☆18Updated 5 years ago
• PeterOgden / PYNQ_image
  Scripts to automate the process of building an image for the Xilinx PYNQ project. This repository is deprecated as its functionality is n…
  ☆20Updated 7 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆35Updated 5 years ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆40Updated 7 years ago
• Digilent / Genesys2
  ☆12Updated 6 years ago
• Digilent / ZYBO
  ☆61Updated 7 years ago
• open-design / riscv-soc-cores
  ☆37Updated 3 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆42Updated 9 years ago
• AEW2015 / PYNQ_PR_Overlay
  Adding PR to the PYNQ Overlay
  ☆17Updated 7 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 3 years ago
• ATaylorCEngFIET / MicroZed-Chronicles
  Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog
  ☆189Updated 6 years ago
• ATaylorCEngFIET / UltraZed-Edition
  UltraZed Edition examples
  ☆12Updated 7 years ago
• snikrepmada / Zynq_Project
  Zynq project to interface OV2640 camera module
  ☆16Updated 8 years ago
• mjlyons / vSPI
  Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah…
  ☆41Updated 3 weeks ago
• suoto / fpga_cores
  ☆32Updated last year
• paulscherrerinstitute / xvcSupport
  ☆17Updated 4 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆57Updated last year
• Digilent / Zybo-Z7-20-pcam-5c
  ☆54Updated 2 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆32Updated 6 years ago
• nelsoncsc / sv_image
  Reusable image processing modules in SystemVerilog
  ☆33Updated 7 years ago
• hamsternz / ArtyEtherentTX
  Sending raw data from the Digilent Arty FPGA board
  ☆22Updated 8 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆31Updated 3 years ago
• jsyk / miilink
  Connecting FPGA and MCU using Ethernet RMII
  ☆22Updated 9 years ago
• DigilentInc / u-boot-Digilent-Dev
  The official Xilinx u-boot repository
  ☆7Updated 6 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆58Updated 2 years ago