A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S defaults to 8 bits and AXI-MM to 64 bits)
☆16Aug 29, 2018Updated 7 years ago
Alternatives and similar repositories for snickerdoodle-hls-data-mover
Users that are interested in snickerdoodle-hls-data-mover are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- snickerdoodle Linux☆18Sep 10, 2018Updated 7 years ago
- an sata controller using smallest resource.☆17Feb 5, 2014Updated 12 years ago
- IP Cores that can be used within Vivado☆27May 18, 2021Updated 4 years ago
- Asynchronous FIFO for FPGAs☆12Mar 20, 2018Updated 8 years ago
- MIDI synthesizer written in VHDL☆13Apr 3, 2012Updated 13 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Tutorial on how to use the AXI ACP on the UltraZed-EG IOCC☆11Jun 13, 2018Updated 7 years ago
- ☆49Dec 10, 2019Updated 6 years ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 2 weeks ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 9 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- Interface Xilinx XDMA PCIe with DDR3 using MIG-IP on Artix-7 FPGA using Nitefury dev board☆18Apr 13, 2022Updated 3 years ago
- LightWeight IP Application Examples for Xilinx FPGA☆15Jan 19, 2016Updated 10 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 3 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 8 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- PCIe DMA Subsystem based on Xilinx XAPP1171☆48Jun 6, 2023Updated 2 years ago
- ☆18Jul 9, 2025Updated 8 months ago
- VHDL implementation of carrier phase recovery (CPR) techniques for coherent optical systems☆16Dec 6, 2020Updated 5 years ago
- Works in Progress and Experiments for the Innova-2 Flex XCKU15P-based Board☆18Apr 4, 2024Updated last year
- Demonstration of the AXI DMA engine on the MicroZed☆26Feb 26, 2021Updated 5 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 7 years ago
- FPGA Development toolset☆20Jun 15, 2017Updated 8 years ago
- JESD204B core for Migen/MiSoC☆36May 5, 2021Updated 4 years ago
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆13Aug 14, 2020Updated 5 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Example projects for snickerdoodle☆29Jan 23, 2026Updated 2 months ago
- My personal Electronics projects versioning repo.☆13Dec 9, 2013Updated 12 years ago
- TCL framework to package Vivado IP-Cores☆14May 18, 2022Updated 3 years ago
- A complete Linux project for the ZYBO. This project helps me during my first steps with embedded Linux. You can find anything necessary t…☆13Oct 8, 2020Updated 5 years ago
- ☆18Sep 16, 2020Updated 5 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 7 years ago
- Cobra-W -> Cobra-RE 将进一步提升漏洞发现的准确性并降低漏报率（弃坑了）☆16Aug 15, 2020Updated 5 years ago
- Designing Relocatable FPGA Partitions with Vivado Design Suite☆10Apr 20, 2018Updated 7 years ago
- Wishbone to AXI bridge (VHDL)☆45Aug 29, 2019Updated 6 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- This is Max's blog, something interesting in it.☆13Jan 1, 2023Updated 3 years ago
- cryptography ip-cores in vhdl / verilog☆41Feb 20, 2021Updated 5 years ago
- ☆89May 4, 2017Updated 8 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆336Jan 20, 2025Updated last year
- The programming runtime and interfaces for ARENA.☆14Sep 14, 2021Updated 4 years ago
- ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor☆11Aug 23, 2017Updated 8 years ago
- The FPGA design for the FreeSRP's Artix 7 FPGA☆26Apr 12, 2017Updated 8 years ago