Alternatives and similar repositories for Verilog-FIR:

Users that are interested in Verilog-FIR are comparing it to the libraries listed below

• RedFlag2017 / rs-codec
  Reed Solomon Encoder and Decoder Digital IP
  ☆19Updated 4 years ago
• maxs-well / LMS-sound-filtering-by-Verilog
  LMS sound filtering by Verilog
  ☆39Updated 5 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆36Updated 3 years ago
• ajackevic / ELEC5882
  The Design and Implementation of a Pulse Compression Filter on an FPGA.
  ☆29Updated 3 years ago
• DexWen / LMS-Adaptive-filter
  LMS-Adaptive Filter implement using verilog and Matlab
  ☆42Updated 8 years ago
• maxs-well / FIR_Implementation
  FIR filter implementation
  ☆26Updated 5 years ago
• hibagus / 64pointFFTProcessor
  Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
  ☆30Updated 4 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆63Updated 8 months ago
• mnmhdanas / DA-Based-LMS-Adaptive-filter
  Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…
  ☆15Updated 3 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆56Updated 2 years ago
• trivedidvijen / SPI-to-I2C-Protocol-Conversion-Using-Verilog
  SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.
  ☆9Updated 3 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆88Updated 3 years ago
• srohit0 / CORDIC
  CORDIC VLSI-IP for deep learning activation functions
  ☆14Updated 5 years ago
• liuguangxi / wifi_ldpc_codec
  Wi-Fi LDPC codec Verilog IP core
  ☆17Updated 5 years ago
• JoshuaEbenezer / FFT-cordic-HDL
  FFT implementation using CORDIC algorithm written in Verilog.
  ☆32Updated 6 years ago
• yaseensalah / Digital-Design-of-FIR-Filter
  Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Veril…
  ☆23Updated 2 years ago
• Noris4est / I2C-FPGA-Verilog-HDL
  In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…
  ☆17Updated 5 years ago
• JoseIuri / axi4lite2uart
  This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.
  ☆20Updated 6 years ago
• red435 / verilog_APB_SPI_interface
  SPI interface connect to APB BUS with Verilog HDL
  ☆31Updated 3 years ago
• cterrill26 / FPGA_AudioVisualizer
  Verilog code for an efficient and scalable DFT calculator (using the FFT algorithm). Meant to be implemented on an Intel DE10-Lite FPGA d…
  ☆14Updated 4 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆33Updated 3 years ago
• fengyulin1996 / Verilog-DSP
  FIR，FFT based on Verilog
  ☆13Updated 7 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆55Updated 8 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆25Updated 4 years ago
• brown9804 / PCIe_physical_layer
  Implementation of the PCIe physical layer
  ☆39Updated 3 months ago
• lauchinyuan / FPGA_DDR3_Ctrl
  An AXI DDR3 SDRAM controller for FPGA
  ☆36Updated last year
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆53Updated 3 years ago
• PXVI / ip_amba_apb_ms_rtl_v
  The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )
  ☆14Updated 2 years ago
• DeamonYang / FPGA_SYNC_ASYNC_FIFO
  FPGA 同步FIFO与异步FIFO
  ☆30Updated 6 years ago