CospanDesign / nysa-verilogLinks
Verilog Repository for GIT
☆34Updated 4 years ago
Alternatives and similar repositories for nysa-verilog
Users that are interested in nysa-verilog are comparing it to the libraries listed below
Sorting:
- IP Cores that can be used within Vivado☆27Updated 4 years ago
- Sata 2 Host Controller for FPGA implementation☆18Updated 8 years ago
- USB 2.0 Device IP Core☆72Updated 8 years ago
- SPI-Flash XIP Interface (Verilog)☆47Updated 4 years ago
- Small (Q)SPI flash memory programmer in Verilog☆67Updated 3 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 5 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Updated 8 years ago
- TCP/IP controlled VPI JTAG Interface.☆69Updated 11 months ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- Verilog I2C Slave☆24Updated 11 years ago
- USB 1.1 Host and Function IP core☆24Updated 11 years ago
- ☆89Updated 8 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆52Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- USB Full Speed PHY☆48Updated 5 years ago
- Module giải mã và đóng gói cho các giao thức IP/TCP+UDP. Viết bằng Verilog. Đề tài thực hiện cho Đồ án thiết kế luận lý.☆13Updated 3 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- Video Stream Scaler☆40Updated 11 years ago
- MMC (and derivative standards) host controller☆25Updated 5 years ago
- ☆30Updated 8 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- Testbenches for HDL projects☆22Updated this week
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆21Updated 8 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 10 years ago
- USB -> AXI Debug Bridge☆41Updated 4 years ago
- SDIO Device Verilog Core☆23Updated 7 years ago
- Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters☆11Updated 12 years ago
- AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP☆13Updated 2 years ago