Elphel / x393Links
mirror of https://git.elphel.com/Elphel/x393
☆40Updated 2 years ago
Alternatives and similar repositories for x393
Users that are interested in x393 are comparing it to the libraries listed below
Sorting:
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 10 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 5 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated last month
- Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces☆35Updated last year
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Updated 2 years ago
- Open Processor Architecture☆26Updated 9 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated last week
- Generic Logic Interfacing Project☆48Updated 5 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆32Updated 8 years ago
- ☆63Updated 7 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆100Updated 6 years ago
- Small footprint and configurable JESD204B core☆50Updated last week
- Extensible FPGA control platform☆61Updated 2 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- OpenFPGA☆34Updated 7 years ago
- An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.☆51Updated 12 years ago
- Torc: Tools for Open Reconfigurable Computing☆39Updated 8 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆47Updated last year
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆41Updated 10 years ago
- a playground for xilinx zynq fpga experiments☆49Updated 7 years ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Wishbone to AXI bridge (VHDL)☆44Updated 6 years ago
- Collection of hardware description languages writings and code snippets☆28Updated 10 years ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Updated 10 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- USB 1.1 Device IP Core☆21Updated 8 years ago
- A Tcl-based CAD Tool Framework for Xilinx's Vivado Design Suite☆44Updated 6 years ago
- LatticeMico32 soft processor☆107Updated 11 years ago