Elphel / x393

Related projects ⓘ

Alternatives and complementary repositories for x393

• Elphel / x393_sata
  mirror of https://git.elphel.com/Elphel/x393_sata
  ☆33Updated 4 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆42Updated 9 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated last year
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆60Updated 2 weeks ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆35Updated 5 years ago
• Elphel / vdt-plugin
  mirror of https://git.elphel.com/Elphel/vdt-plugin
  ☆15Updated 6 years ago
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆44Updated 4 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆53Updated last year
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• jsloan256 / titan
  Altium PCB project for the Titan PCI Express development card. This card uses the Lattice ECP5 FPGA.
  ☆19Updated 9 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• swetland / zynq-sandbox
  a playground for xilinx zynq fpga experiments
  ☆48Updated 5 years ago
• linuxbest / ahci_mpi
  an sata controller using smallest resource.
  ☆15Updated 10 years ago
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆34Updated 7 years ago
• blackmesalabs / MesaBusProtocol
  Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces
  ☆28Updated 7 years ago
• jerry-D / SYMPL-GP-GPU-Compute-Engines
  Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…
  ☆22Updated 5 years ago
• maltevesper / JetStream-driver
  ☆15Updated 8 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆33Updated 6 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆40Updated last month
• jck / riscv
  ☆20Updated 10 months ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 5 years ago
• ThalesGroup / TMR
  Triple Modular Redundancy
  ☆23Updated 5 years ago
• nelsoncsc / sv_image
  Reusable image processing modules in SystemVerilog
  ☆33Updated 7 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆54Updated last month
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆17Updated 12 years ago
• FeldmeierMichael / MIPI_CSI_2
  ☆13Updated last year
• cfelton / test_jpeg
  This is a myhdl test environment for the open-cores jpeg_encoder.
  ☆16Updated 8 years ago
• daveshah1 / ElasticC
  lightweight open HLS for FPGA rapid prototyping
  ☆20Updated 6 years ago
• maltevesper / JetStream-hardware
  ☆22Updated 8 years ago