Elphel / x393
mirror of https://git.elphel.com/Elphel/x393
☆38Updated last year
Alternatives and similar repositories for x393:
Users that are interested in x393 are comparing it to the libraries listed below
- Fork of OpenCores jpegencode with Cocotb testbench☆42Updated 9 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆35Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 4 years ago
- Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces☆30Updated 2 months ago
- a playground for xilinx zynq fpga experiments☆48Updated 6 years ago
- ☆15Updated 8 years ago
- Extensible FPGA control platform☆57Updated last year
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated this week
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- lightweight open HLS for FPGA rapid prototyping☆20Updated 6 years ago
- an sata controller using smallest resource.☆15Updated 11 years ago
- OpenCL Demos for Xilinx FPGAs☆31Updated 9 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Open Hardware carrier board supporting modules with Zynq 7000 All Programmable SoC devices.☆56Updated last year
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- ☆63Updated 6 years ago
- MIPI CSI-2 RX☆31Updated 3 years ago
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆29Updated 4 years ago
- DyRACT Open Source Repository☆16Updated 8 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 7 months ago
- mirror of https://git.elphel.com/Elphel/vdt-plugin☆15Updated 7 years ago
- Small footprint and configurable JESD204B core☆41Updated last month
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- hdmi-ts Project☆13Updated 7 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 4 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆39Updated 9 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 6 years ago
- Altera Cyclone IV FPGA project for the PCIe LimeSDR board☆37Updated 2 years ago
- ☆19Updated last year
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year