CospanDesign / nysaLinks
FPGA Development toolset
☆20Updated 8 years ago
Alternatives and similar repositories for nysa
Users that are interested in nysa are comparing it to the libraries listed below
Sorting:
- Small footprint and configurable Inter-Chip communication cores☆66Updated 2 months ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Updated 7 years ago
- RISC-V processor☆32Updated 3 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆31Updated 5 years ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- ☆27Updated 10 months ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 4 years ago
- MyBlaze is a synthesizable clone of the MicroBlaze Soft Processor written in MyHDL (http://www.myhdl.org). It started as a translation of…☆17Updated 12 years ago
- System on Chip toolkit for nMigen☆19Updated 5 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- Example of how to use UVM with Verilator☆31Updated last month
- Cross compile FPGA tools☆21Updated 5 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Updated 2 years ago
- Demo SoC for SiliconCompiler.☆62Updated this week
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 4 years ago
- A cross platform, formally verified, open source, hyperRAM controller with simulator☆14Updated 6 years ago
- ☆20Updated 3 years ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆22Updated 6 years ago
- Generic Logic Interfacing Project☆48Updated 5 years ago
- Small footprint and configurable video cores (Deprecated)☆73Updated 4 years ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Updated 10 years ago
- SoftCPU/SoC engine-V☆55Updated 9 months ago
- Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)☆21Updated 9 years ago
- Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…☆12Updated 6 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated 3 weeks ago
- Next-Generation FPGA Place-and-Route☆10Updated 7 years ago
- OpenFPGA☆34Updated 7 years ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 7 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆47Updated 3 weeks ago
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆31Updated 5 years ago