Yosys RTLIL dialect for MLIR
☆24Jun 12, 2025Updated last year
Alternatives and similar repositories for rtlil-mlir
Users that are interested in rtlil-mlir are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- APS: An open-source toolchain towards agile processor specialization based on MLIR☆20Jan 17, 2026Updated 7 months ago
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆13Mar 27, 2025Updated last year
- Code for the paper "LLM Meets Bounded Model Checking: Neuro-symbolic Loop Invariant Inference" at ASE 2024☆30Sep 3, 2024Updated last year
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- Contract-Aware RTL Code Generation Agents with Temporal Tracing, Slicing and Formal Verification☆24Jan 28, 2026Updated 7 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A Lean-embedded framework to verify Verilog modules☆15Aug 15, 2026Updated 2 weeks ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 9 months ago
- DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)☆14Nov 2, 2023Updated 2 years ago
- ☆17Mar 26, 2025Updated last year
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆17Aug 13, 2022Updated 4 years ago
- ☆14Jan 3, 2018Updated 8 years ago
- 21st century electronic design automation tools, written in Rust.☆37Updated this week
- Equivalence checking with Yosys☆61Aug 5, 2026Updated 3 weeks ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Jul 26, 2023Updated 3 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- (WIP) Open-source Rust gate-level EDA infrastructure: parsers and databases☆21May 2, 2026Updated 3 months ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated 2 years ago
- E-Graphs, natively in MLIR☆36Updated this week
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.☆15Nov 19, 2024Updated last year
- ☆32Nov 2, 2025Updated 9 months ago
- TAIDL: Tensor Accelerator ISA Definition Language☆19Apr 28, 2026Updated 4 months ago
- ☆13Jan 20, 2023Updated 3 years ago
- AI-Assisted Verification of Data Structures☆22May 27, 2026Updated 3 months ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆39Jan 26, 2026Updated 7 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆45Jul 17, 2024Updated 2 years ago
- E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)☆31Jun 23, 2025Updated last year
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆30Apr 9, 2025Updated last year
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆32May 24, 2025Updated last year
- The HW-CBMC and EBMC Model Checkers for Verilog☆114Updated this week
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆35Aug 25, 2024Updated 2 years ago
- Source code for Trinity(ASPLOS 2026)☆26Apr 24, 2026Updated 4 months ago
- C++ implementation of FRAIGs. Won the 1st place in 2018 Cadence-sponsored contest in NTU DSnP.☆10Oct 21, 2020Updated 5 years ago
- Rust bindings for CIRCT☆18Apr 20, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- CODO: An Automated Compiler for Comprehensive Dataflow Optimization☆36Jun 3, 2026Updated 2 months ago
- ☆20Jan 2, 2026Updated 7 months ago
- rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission☆12Jul 4, 2025Updated last year
- ☆49May 18, 2024Updated 2 years ago
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- A collection of datapath circuit design and verification benchmarks☆19Updated this week
- ☆15Dec 9, 2025Updated 8 months ago