A Coq framework to support structural design and proof of hardware cache-coherence protocols
☆15May 7, 2022Updated 4 years ago
Alternatives and similar repositories for hemiola
Users that are interested in hemiola are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆11Nov 19, 2015Updated 10 years ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 3 years ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 11 months ago
- RTLCheck☆26Oct 9, 2018Updated 8 years ago
- Safe high-level bindings for the Boolector SMT solver☆14Apr 5, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆16Sep 14, 2020Updated 6 years ago
- Certify Model Checking Witnesses in AIGER☆14Oct 16, 2026Updated 2 weeks ago
- Very tiny embeddable Tcl-like language in safe Rust☆12Feb 13, 2025Updated last year
- ☆14Sep 27, 2026Updated last month
- ☆15Feb 6, 2021Updated 5 years ago
- A DSL for formal verification of hardware and software systems using Rocq/Coq.☆12Updated this week
- A simple induction and BMC engine.☆25May 16, 2022Updated 4 years ago
- ☆13May 7, 2026Updated 5 months ago
- Easy SMT solver interaction☆37Feb 3, 2026Updated 8 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission☆12Jul 4, 2025Updated last year
- Wishbone plumbing written in Chisel3☆10Dec 19, 2024Updated last year
- Open stadard cell library for open 28nm process☆18Jul 5, 2023Updated 3 years ago
- ☆21Dec 29, 2014Updated 11 years ago
- ☆16Mar 18, 2025Updated last year
- A prototype SMT-solver for the theory of bit-vectors and uninterpreted functions.☆10Dec 10, 2023Updated 2 years ago
- BuDDy Binary Decision Diagram(BDD) library provisioned with CMake files☆14Apr 1, 2017Updated 9 years ago
- A Lean-embedded framework to verify Verilog modules☆17Oct 6, 2026Updated 3 weeks ago
- Verified Verilog Equivalence checker, written and verified in Coq.☆14Oct 20, 2026Updated last week
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Equivalence checking with Yosys☆66Oct 20, 2026Updated last week
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆14Mar 27, 2025Updated last year
- A LNCS template for typst☆17Jun 15, 2026Updated 4 months ago
- A programming language for writing constraint-based integrated circuit layout generators☆17Updated this week
- Tools for reasoning about circuits in Rosette/Racket 🔌☆20Feb 1, 2025Updated last year
- A tiny 3-stage RISC-V core written in Chisel.☆18Apr 14, 2023Updated 3 years ago
- llm-powered theorem proving for isabelle/hol☆16Jul 22, 2026Updated 3 months ago
- SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.☆16Aug 30, 2023Updated 3 years ago
- https://conf.researchr.org/details/icfp-splash-2025/icfp-splash-2025-tutorials/5/A-guided-tour-through-Oxidized-OCaml☆22Jun 18, 2026Updated 4 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A fork of Yosys that integrates the CellIFT pass☆14Sep 12, 2026Updated last month
- Typst template for thesis submitted to University of Waterloo☆11Feb 21, 2026Updated 8 months ago
- A collection of datapath circuit design and verification benchmarks☆19Aug 24, 2026Updated 2 months ago
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 6 years ago
- ☆18Nov 9, 2022Updated 3 years ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆117Oct 23, 2026Updated last week
- Testing processors with Random Instruction Generation☆63Oct 5, 2026Updated 3 weeks ago