CASR-HKU / ESDALinks
☆11Updated last year
Alternatives and similar repositories for ESDA
Users that are interested in ESDA are comparing it to the libraries listed below
Sorting:
- ☆21Updated 2 years ago
- ☆26Updated 2 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 3 years ago
- ☆20Updated 3 years ago
- ☆17Updated 2 years ago
- ☆32Updated 4 years ago
- A DAG processor and compiler for a tree-based spatial datapath.☆14Updated 3 years ago
- Offical implementation of High-Performance Temporal Reversible Spiking Neural Networks with $O(L)$ Training Memory and $O(1)$ Inference C…☆22Updated 4 months ago
- This is the official implementation of the 'SFOD: Spiking Fusion Object Detection'.☆34Updated last year
- Object Detection Based on Dynamic Vision Sensor with Spiking Neural Network☆19Updated 2 years ago
- This is the entry project of the Xilinx Adaptive Computing Challenge 2021. It uses YOLOv3 for ship target detection in optical remote sen…☆17Updated 3 years ago
- Hardware Acceleration of Neural Networks for Event Camera-Based Object Detection on SoC FPGAs☆15Updated last month
- Pytorch implementation of SEENN (Spiking Early Exit Neural Networks) (NeurIPS 2023)☆15Updated 10 months ago
- LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks, MICRO 2024.☆13Updated 6 months ago
- ☆17Updated 4 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆61Updated 4 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- ☆30Updated 6 months ago
- My name is Fang Biao. I'm currently pursuing my Master degree with the college of Computer Science and Engineering, Si Chuan University, …☆53Updated 2 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- ☆18Updated 2 years ago
- 🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*☆20Updated last year
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆11Updated 5 years ago
- Vivado HLS implementation of EDFLOW IP☆15Updated 3 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Updated 2 years ago
- Deployment of Deep learning Image Super-Resolution Models in Xilinx Zynq MPSoC ZCU102☆16Updated 5 years ago
- ☆16Updated 3 years ago
- Vitis AI Lab: MNIST classifier☆19Updated 3 years ago
- [CVPR 2024] Offical implementation for A&B BNN: Add&Bit-Operation-Only Hardware-Friendly Binary Neural Network☆24Updated 9 months ago
- A programming framework based on PyTorch for hybrid neural networks with automatic quantization☆20Updated last year