hVHDL / hVHDL_floating_pointLinks
high level VHDL floating point library for synthesis in fpga
☆18Updated 6 months ago
Alternatives and similar repositories for hVHDL_floating_point
Users that are interested in hVHDL_floating_point are comparing it to the libraries listed below
Sorting:
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated last week
- VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and …☆23Updated last week
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆23Updated last year
- Library of reusable VHDL components☆28Updated last year
- Fixed-point math library with VHDL, Python and MATLAB support☆27Updated 2 weeks ago
- Groundhog - Serial ATA Host Bus Adapter☆24Updated 7 years ago
- CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules☆11Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Repository containing the DSP gateware cores☆13Updated this week
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆64Updated last month
- Open FPGA Modules☆24Updated 10 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆24Updated last month
- UART models for cocotb☆29Updated 2 years ago
- ☆32Updated 2 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆64Updated 2 weeks ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆57Updated 3 weeks ago
- WISHBONE Interconnect☆11Updated 7 years ago
- Triple Modular Redundancy☆27Updated 5 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆29Updated last year
- Extensible FPGA control platform☆62Updated 2 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆28Updated last year
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- general-cores☆20Updated last month
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- ☆33Updated 2 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆34Updated 6 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- VHDLproc is a VHDL preprocessor