UCLA-VAST / soda-compilerLinks
Stencil with Optimized Dataflow Architecture Compiler
☆17Updated 5 years ago
Alternatives and similar repositories for soda-compiler
Users that are interested in soda-compiler are comparing it to the libraries listed below
Sorting:
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- ☆24Updated 4 years ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- ☆26Updated 3 years ago
- ☆33Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆81Updated last year
- EQueue Dialect☆40Updated 3 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆72Updated 6 years ago
- ☆41Updated 11 months ago
- A high-level performance analysis tool for FPGA-based accelerators☆20Updated 8 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆124Updated 5 years ago
- MAESTRO binary release☆23Updated 5 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆53Updated 2 months ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- agile hardware-software co-design☆48Updated 3 years ago
- A Generic Distributed Auto-Tuning Infrastructure☆22Updated 3 years ago
- ☆10Updated 2 years ago
- Heterogenous ML accelerator☆18Updated last month
- A DSL for Systolic Arrays☆79Updated 6 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- ☆28Updated 2 years ago
- ☆16Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆92Updated 8 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 3 months ago
- NeuraChip Accelerator Simulator☆12Updated last year
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆50Updated 6 years ago
- ☆29Updated 6 years ago