Alternatives and similar repositories for soda-compiler:

Users that are interested in soda-compiler are comparing it to the libraries listed below

• zhguanw / lin-analyzer
  A high-level performance analysis tool for FPGA-based accelerators
  ☆19Updated 7 years ago
• he-actlab / planaria.code
  ☆25Updated 3 years ago
• kartik-hegde / mindmappings
  A reference implementation of the Mind Mappings Framework.
  ☆29Updated 3 years ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆30Updated 3 years ago
• maestro-project / confuciux
  ☆32Updated 3 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 2 years ago
• cucapra / EventQueue
  EQueue Dialect
  ☆40Updated 3 years ago
• UCLA-VAST / hbmbench
  ☆23Updated 4 years ago
• PrincetonUniversity / accelerator-wall
  Repository for the tools and non-commercial data used for the "Accelerator wall" paper.
  ☆49Updated 6 years ago
• cdsc-github / parade-ara-simulator
  PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration
  ☆48Updated 2 years ago
• cornell-zhang / uptune
  A Generic Distributed Auto-Tuning Infrastructure
  ☆22Updated 3 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆69Updated 5 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆64Updated 3 years ago
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆79Updated last year
• hyoukjun / MAESTRO
  MAESTRO binary release
  ☆22Updated 5 years ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆120Updated 4 years ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆79Updated 6 years ago
• pku-liang / HASCO
  agile hardware-software co-design
  ☆47Updated 3 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆28Updated last year
• template-hls / template-hls-float
  ☆27Updated 5 years ago
• xuanyoya / Interstellar-CNN-scheduler
  Tool for optimize CNN blocking
  ☆94Updated 4 years ago
• Xilinx / merlin-compiler
  ☆57Updated last year
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 2 years ago
• Accelergy-Project / processing-in-memory-design
  ☆26Updated 11 months ago
• maestro-project / gamma
  ☆39Updated 8 months ago
• maeri-project / MAERI_bsv_isca2018
  MAERI public release
  ☆31Updated 3 years ago
• maestro-project / magma
  ☆16Updated 2 years ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆50Updated 2 weeks ago
• sfu-arch / SpGEMM
  ☆34Updated 3 years ago