UCLA-VAST / soda-compiler
Stencil with Optimized Dataflow Architecture Compiler
☆16Updated 4 years ago
Alternatives and similar repositories for soda-compiler:
Users that are interested in soda-compiler are comparing it to the libraries listed below
- ☆25Updated 3 years ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- ☆32Updated 3 years ago
- ☆23Updated 4 years ago
- EQueue Dialect☆40Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- A high-level performance analysis tool for FPGA-based accelerators☆19Updated 7 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆66Updated 5 years ago
- MAESTRO binary release☆22Updated 5 years ago
- A Generic Distributed Auto-Tuning Infrastructure☆21Updated 3 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆48Updated 3 weeks ago
- ☆39Updated 7 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆60Updated 3 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- agile hardware-software co-design☆47Updated 3 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆57Updated 4 months ago
- ☆25Updated 9 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆41Updated this week
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆23Updated 2 months ago
- Tool for optimize CNN blocking☆93Updated 4 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆117Updated 4 years ago
- QuickEst repository: Quick Estimation of Quality of Results☆26Updated 6 years ago
- ☆57Updated last year
- MICRO22 artifact evaluation for Sparseloop☆41Updated 2 years ago
- ☆42Updated 10 months ago
- ☆34Updated 3 years ago
- ☆11Updated last year