jonathan93sh / CNNA
A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA
☆22Updated 3 years ago
Alternatives and similar repositories for CNNA:
Users that are interested in CNNA are comparing it to the libraries listed below
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated last year
- Some attempts to build CNN on PYNQ.☆24Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆47Updated 6 years ago
- 2020 xilinx summer school☆17Updated 4 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆9Updated 4 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆30Updated 5 years ago
- CNN Accelerator in Frequency Domain☆12Updated 4 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆34Updated 5 years ago
- ☆26Updated 2 years ago
- Codes to implement MobileNet V2 in a FPGA☆24Updated 4 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆55Updated 3 years ago
- A DNN Accelerator implemented with RTL.☆63Updated last month
- This project implements a convolution kernel based on vivado HLS on zcu104☆36Updated 4 years ago
- A collection of tutorials for the fpgaConvNet framework.☆38Updated 4 months ago
- ☆27Updated 3 months ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 3 years ago
- hls code zynq 7020 pynq z2 CNN☆79Updated 5 years ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆14Updated 3 years ago
- Designs for finalist teams of the DAC System Design Contest☆36Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆43Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆9Updated 3 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆31Updated 5 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆19Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆35Updated 2 years ago