MartaAndronic / PolyLUT
PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial function learning to exploit the flexibility of the FPGA soft logic.
☆51Updated last year
Alternatives and similar repositories for PolyLUT:
Users that are interested in PolyLUT are comparing it to the libraries listed below
- NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions☆29Updated last month
- A collection of tutorials for the fpgaConvNet framework.☆39Updated 7 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated last week
- ☆57Updated 5 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆40Updated last year
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆31Updated this week
- ☆26Updated last month
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆140Updated this week
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆52Updated 3 months ago
- Implementation of Microscaling data formats in SystemVerilog.☆17Updated 8 months ago
- Open-source of MSD framework☆16Updated last year
- An FPGA Accelerator for Transformer Inference☆81Updated 3 years ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆29Updated 5 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆34Updated last week
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆76Updated 3 years ago
- ☆43Updated 2 years ago
- ☆15Updated 10 months ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆49Updated last month
- ☆35Updated last month
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆58Updated 3 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆51Updated last month
- ☆23Updated 2 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆76Updated last week
- ☆91Updated 10 months ago
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆21Updated 5 months ago
- A bit-level sparsity-awared multiply-accumulate process element.☆15Updated 9 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆38Updated 2 years ago
- ☆71Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 9 months ago