MartaAndronic / PolyLUT
PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial function learning to exploit the flexibility of the FPGA soft logic.
☆49Updated last year
Alternatives and similar repositories for PolyLUT:
Users that are interested in PolyLUT are comparing it to the libraries listed below
- NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions☆19Updated 11 months ago
- A collection of tutorials for the fpgaConvNet framework.☆40Updated 5 months ago
- Implementation of Microscaling data formats in SystemVerilog.☆14Updated 6 months ago
- ☆71Updated 2 years ago
- ☆57Updated 4 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆29Updated 7 months ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆36Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆46Updated 5 months ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆36Updated last month
- Open-source of MSD framework☆16Updated last year
- Verilog implementation of Softmax function☆57Updated 2 years ago
- ☆25Updated 2 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆130Updated 2 months ago
- ☆23Updated 2 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆48Updated 3 weeks ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆37Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆69Updated 3 years ago
- ☆39Updated last year
- An FPGA Accelerator for Transformer Inference☆78Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆77Updated 7 months ago
- ☆10Updated 3 months ago
- RTL implementation of Flex-DPE.☆98Updated 5 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆56Updated 3 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆32Updated last year
- The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …☆123Updated last year
- ☆33Updated last week
- ☆84Updated 9 months ago