MartaAndronic / PolyLUTLinks
PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial function learning to exploit the flexibility of the FPGA soft logic.
☆53Updated last year
Alternatives and similar repositories for PolyLUT
Users that are interested in PolyLUT are comparing it to the libraries listed below
Sorting:
- NeuraLUT-Assemble☆41Updated 2 months ago
- A collection of tutorials for the fpgaConvNet framework.☆45Updated last year
- ☆60Updated 5 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆87Updated last year
- ☆29Updated 6 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆60Updated 3 months ago
- ☆72Updated 2 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆67Updated last month
- Implementation of Microscaling data formats in SystemVerilog.☆26Updated 3 months ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆95Updated this week
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆157Updated this week
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- Train and deploy LUT-based neural networks on FPGAs☆99Updated last year
- Library of approximate arithmetic circuits☆55Updated 3 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 8 months ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 4 years ago
- An FPGA Accelerator for Transformer Inference☆91Updated 3 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆98Updated 9 months ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- ☆44Updated 2 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆175Updated 2 months ago
- SAMO: Streaming Architecture Mapping Optimisation☆34Updated 2 years ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆162Updated 2 months ago
- ☆22Updated 3 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆33Updated this week
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆40Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆81Updated 3 years ago
- RTL implementation of Flex-DPE.☆113Updated 5 years ago
- ☆37Updated 7 months ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆52Updated last year