MartaAndronic / PolyLUTLinks
PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial function learning to exploit the flexibility of the FPGA soft logic.
☆55Updated last year
Alternatives and similar repositories for PolyLUT
Users that are interested in PolyLUT are comparing it to the libraries listed below
Sorting:
- NeuraLUT-Assemble☆47Updated 5 months ago
- ☆65Updated 5 years ago
- A collection of tutorials for the fpgaConvNet framework.☆47Updated last year
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 4 years ago
- ☆72Updated 2 years ago
- ☆32Updated 9 months ago
- Implementation of Microscaling data formats in SystemVerilog.☆29Updated 6 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated this week
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆104Updated 2 weeks ago
- Train and deploy LUT-based neural networks on FPGAs☆106Updated last year
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Updated 11 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- ☆45Updated this week
- Open-source of MSD framework☆16Updated 2 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆34Updated 2 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆119Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆84Updated 4 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆97Updated 4 years ago
- An FPGA Accelerator for Transformer Inference☆92Updated 3 years ago
- Verilog implementation of Softmax function☆78Updated 3 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆35Updated this week
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 6 months ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆33Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆74Updated 2 months ago
- ☆22Updated 3 years ago
- ☆72Updated 7 years ago
- ☆35Updated 6 years ago
- An LSTM template and a few examples using Vivado HLS☆47Updated last year
- ☆46Updated 2 years ago