verilator / example-systemverilog

Related projects ⓘ

Alternatives and complementary repositories for example-systemverilog

• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆35Updated 6 months ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆59Updated 3 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆43Updated 2 years ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆30Updated 3 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆25Updated 4 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 6 months ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆54Updated 4 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆45Updated 5 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆54Updated last year
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆50Updated 4 years ago
• pulp-platform / axi_spi_master
  ☆20Updated 5 years ago
• chipsalliance / uvm-verilator
  ☆75Updated last year
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆43Updated 11 months ago
• oprecomp / DDR4_controller
  ☆47Updated 3 years ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆15Updated 6 months ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆48Updated 6 months ago
• pulp-platform / axi_spi_slave
  ☆23Updated 3 years ago
• mitya1337 / Simple_I2C
  Simple implementation of I2C interface written on Verilog and SystemC
  ☆37Updated 7 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆51Updated last year
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆32Updated 3 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆58Updated 4 years ago
• freecores / jtag
  JTAG Test Access Port (TAP)
  ☆30Updated 10 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆29Updated 3 years ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆32Updated 8 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆28Updated last month
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆32Updated last year
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆58Updated 2 years ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆40Updated 4 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆25Updated 3 weeks ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆49Updated 4 years ago