Alternatives and similar repositories for example-systemverilog

Users that are interested in example-systemverilog are comparing it to the libraries listed below

• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• pulp-platform / axi2apb
  ☆20Updated 5 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆50Updated last year
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆28Updated 8 months ago
• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆57Updated 5 years ago
• pulp-platform / axi_spi_slave
  ☆25Updated 3 years ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆12Updated this week
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆60Updated 4 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆32Updated 4 months ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆61Updated 3 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆39Updated 2 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆55Updated 2 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆52Updated last year
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆65Updated 3 months ago
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆41Updated 11 months ago
• pulp-platform / axi_llc
  ☆29Updated last month
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆67Updated 8 months ago
• freecores / jtag
  JTAG Test Access Port (TAP)
  ☆33Updated 10 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• munetomo-maruyama / mmRISC-1
  RISC-V RV32IMAFC Core for MCU
  ☆37Updated 4 months ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 5 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆32Updated 5 months ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆18Updated 7 years ago