Alternatives and similar repositories for example-systemverilog

Users that are interested in example-systemverilog are comparing it to the libraries listed below

• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆44Updated last year
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 3 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 6 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆68Updated 9 months ago
• chipsalliance / uvm-verilator
  ☆110Updated 3 weeks ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆73Updated 11 months ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆61Updated 2 years ago
• pulp-platform / axi2apb
  ☆21Updated 5 years ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆13Updated 3 months ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆61Updated last year
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 10 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated last month
• aignacio / nox
  RISC-V Nox core
  ☆69Updated 4 months ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆127Updated 2 weeks ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆86Updated 4 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆55Updated 5 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 4 months ago
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆52Updated 4 months ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 10 months ago
• pulp-platform / axi_llc
  ☆32Updated last week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 4 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆143Updated 2 weeks ago
• martinriis / RISC-V-Vector-Processor
  256-bit vector processor based on the RISC-V vector (V) extension
  ☆31Updated 4 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆72Updated 4 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆30Updated last year
• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated 2 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆55Updated last year
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆70Updated 2 months ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆85Updated 4 years ago
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆47Updated last year