RiVer Core is an open source Python based RISC-V Core Verification framework.
☆23Jun 16, 2025Updated 11 months ago
Alternatives and similar repositories for river_core
Users that are interested in river_core are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verification of Ethernet Switch System Verilog☆12Oct 21, 2016Updated 9 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆12Oct 26, 2019Updated 6 years ago
- ☆15Sep 27, 2022Updated 3 years ago
- Network on Chip for MPSoC☆28May 3, 2026Updated 2 weeks ago
- Consistency checker for memory subsystem traces☆23Oct 10, 2016Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement,…☆16Mar 8, 2026Updated 2 months ago
- The RISC-V Application Profiler is a Python-based tool designed to help software developers optimize the performance of their application…☆31Apr 23, 2025Updated last year
- ☆13Aug 22, 2022Updated 3 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Updated this week
- Digital IC design and vlsi notes☆14Jun 24, 2020Updated 5 years ago
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 4 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆19Feb 27, 2025Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- This repo contain the PY-UVM Framework for different RISC-V Cores☆33Sep 16, 2023Updated 2 years ago
- VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation,…☆37Updated this week
- uvm_apb is a uvm package for modeling and verifying APB (Advanced Periperal Bus) protocol☆21Feb 7, 2025Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆102Mar 29, 2024Updated 2 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- Project ideas list for Google Summer of Code.☆18Jan 28, 2026Updated 3 months ago
- Final Project for Digital Systems Design Course, Fall 2020☆17Jul 20, 2022Updated 3 years ago
- An introductory guide to Bluespec (BSV)☆68May 4, 2019Updated 7 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Implementing a RISC-V CPU on FPGA(Cyclone II)☆25Feb 19, 2023Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆192Nov 18, 2024Updated last year
- ☆13May 5, 2023Updated 3 years ago
- YosysHQ SVA AXI Properties☆50Feb 7, 2023Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Jun 28, 2025Updated 10 months ago
- ☆11Jun 11, 2018Updated 7 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 4 years ago
- ☆19Apr 28, 2026Updated 3 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An instruction set simulator based on DBT-RISE implementing the RISC-V ISA☆37May 15, 2026Updated last week
- Hardcaml Verification Tools☆15Apr 6, 2026Updated last month
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆26Jan 1, 2022Updated 4 years ago
- RISCulator is a RISC-V emulator.☆12Aug 18, 2023Updated 2 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- Classify modulation of signals☆16Jan 16, 2020Updated 6 years ago
- My local copy of UVM-SystemC☆14Apr 27, 2024Updated 2 years ago