incoresemi / river_coreLinks
RiVer Core is an open source Python based RISC-V Core Verification framework.
☆22Updated 5 months ago
Alternatives and similar repositories for river_core
Users that are interested in river_core are comparing it to the libraries listed below
Sorting:
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated 8 months ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆14Updated 3 weeks ago
- ☆30Updated 3 weeks ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated 10 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆92Updated last year
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆45Updated last week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated last year
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆21Updated last year
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated last week
- SystemVerilog Functional Coverage for RISC-V ISA☆32Updated 5 months ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- matrix-coprocessor for RISC-V☆25Updated 6 months ago
- The RTL source for AnyCore RISC-V☆33Updated 3 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Updated 3 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated 2 weeks ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 9 months ago
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated last year
- MathLib DAC 2023 version☆13Updated 2 years ago
- This is the base repo for our graduation project in AlexU 21☆28Updated 4 years ago
- ☆15Updated 3 years ago
- DUTH RISC-V Microprocessor☆22Updated 11 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Updated 8 years ago
- IOPMP IP☆21Updated 4 months ago
- ☆27Updated 6 years ago
- Advanced Architecture Labs with CVA6☆70Updated last year