Alternatives and similar repositories for river_core

Users that are interested in river_core are comparing it to the libraries listed below

• comsec-group / mucfi
  Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…
  ☆12Updated 2 months ago
• pulp-platform / axi_llc
  ☆27Updated last month
• armleo / ArmleoCPU
  ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set
  ☆6Updated 2 years ago
• MikeCovrado / GettingVerilatorStartedWithUVM
  Simple UVM environment for experimenting with Verilator.
  ☆20Updated 2 weeks ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆26Updated 2 years ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆32Updated last year
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆33Updated 2 weeks ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated last week
• pulp-platform / ace
  ☆12Updated last month
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 6 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated last year
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆32Updated 3 years ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆37Updated last month
• morenes / AutoCC
  Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…
  ☆17Updated 6 months ago
• RPTU-EIS / upec-boom-verification-suite
  This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…
  ☆17Updated 2 years ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆36Updated last week
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 4 years ago
• zero-day-labs / riscv-iopmp
  IOPMP IP
  ☆14Updated last week
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆28Updated 7 months ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆31Updated last year
• waviousllc / wav-lpddr-sw
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆20Updated 3 years ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆34Updated 4 years ago
• riscv-software-src / riscv-isac
  ☆32Updated 6 months ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆33Updated 3 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• VLSIDA / OpenCache
  An open-source custom cache generator.
  ☆33Updated last year
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆39Updated 2 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆15Updated 3 months ago
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆16Updated 5 years ago
• Open-Source-Hardware-Initiative / AES
  Open Source AES
  ☆31Updated last year