RiVer Core is an open source Python based RISC-V Core Verification framework.
☆23Jun 16, 2025Updated last year
Alternatives and similar repositories for river_core
Users that are interested in river_core are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verification of Ethernet Switch System Verilog☆12Oct 21, 2016Updated 9 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆12Oct 26, 2019Updated 6 years ago
- The RISC-V Application Profiler is a Python-based tool designed to help software developers optimize the performance of their application…☆31Apr 23, 2025Updated last year
- ☆15Sep 27, 2022Updated 3 years ago
- Consistency checker for memory subsystem traces☆23Oct 10, 2016Updated 9 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Network on Chip for MPSoC☆30Aug 7, 2026Updated last month
- A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement,…☆17Mar 8, 2026Updated 6 months ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 7 years ago
- ☆13Aug 22, 2022Updated 4 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 7 years ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆33Sep 16, 2023Updated 3 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆20Feb 27, 2025Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆104Mar 29, 2024Updated 2 years ago
- An introductory guide to Bluespec (BSV)☆69May 4, 2019Updated 7 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Project ideas list for Google Summer of Code.☆18Jan 28, 2026Updated 7 months ago
- Final Project for Digital Systems Design Course, Fall 2020☆17Jul 20, 2022Updated 4 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- Digital IC design and vlsi notes☆15Jun 24, 2020Updated 6 years ago
- uvm_apb is a uvm package for modeling and verifying APB (Advanced Periperal Bus) protocol☆21Feb 7, 2025Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆71Jun 28, 2025Updated last year
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆20Aug 6, 2026Updated last month
- ☆13May 5, 2023Updated 3 years ago
- Developing a Drone from scratch in ROS Gazebo☆15Dec 15, 2021Updated 4 years ago
- RISCulator is a RISC-V emulator.☆12Aug 18, 2023Updated 3 years ago
- ☆12Jun 11, 2018Updated 8 years ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆26Jan 1, 2022Updated 4 years ago
- YosysHQ SVA AXI Properties☆56Feb 7, 2023Updated 3 years ago
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 5 years ago
- Lisa is a tool for (a). An LTLf to DFA conversion, and (b) An LTLf synthesis tool. Lisa supports both explicit and symbolic state-space r…☆13Sep 27, 2021Updated 4 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- An instruction set simulator based on DBT-RISE implementing the RISC-V ISA☆37Updated this week
- Classify modulation of signals☆16Jan 16, 2020Updated 6 years ago
- My local copy of UVM-SystemC☆14Apr 27, 2024Updated 2 years ago
- Project Status: Discontinued, New repository: spec2rtl-plugin☆31Feb 1, 2026Updated 7 months ago
- RISC-V BSV Specification☆24Apr 28, 2026Updated 4 months ago
- Hardcaml Verification Tools☆20Jul 10, 2026Updated 2 months ago
- Hardware Verification library for C++, SystemC and SystemVerilog☆30Nov 27, 2012Updated 13 years ago