Alternatives and similar repositories for jpeg_comp_verilog

Users that are interested in jpeg_comp_verilog are comparing it to the libraries listed below

• open-dv / dma_axi
  ☆16Updated 6 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆29Updated 2 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• CospanDesign / verilog_ppfifo_demo
  Simple demo showing how to use the ping pong FIFO
  ☆15Updated 9 years ago
• ved-rivos / iommu-rtl
  RISC-V IOMMU in verilog
  ☆18Updated 3 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• RPG-7 / HGA101_GPU
  ☆16Updated 4 years ago
• zhouzaixin / arm_soc
  ☆14Updated 6 years ago
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆34Updated 7 years ago
• wmy367 / Radix-2-division
  unsigned Radix-2 SRT division,基2除法
  ☆15Updated 10 years ago
• PacoReinaCampo / MPSoC-NoC
  Network on Chip for MPSoC
  ☆26Updated 2 months ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 9 years ago
• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆34Updated 4 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆11Updated 4 years ago
• PacoReinaCampo / MPSoC-DMA
  Direct Access Memory for MPSoC
  ☆13Updated 2 months ago
• Aquaticfuller / OpenExSys_CoherentCache
  OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.
  ☆14Updated 4 months ago
• zhangkunming0216 / FIFO_-asynchronous
  异步FIFO的内部实现
  ☆24Updated 6 years ago
• pulp-platform / jtag_pulp
  ☆13Updated 2 years ago
• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• forever-gk / AHB-SystemVerilog
  ☆17Updated 10 years ago
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆19Updated 7 years ago
• hankshyu / TaskScheduler
  a hardware task scheduler design
  ☆9Updated 2 years ago
• GuiZhaoCodeSource / Func_Verif_MMU_Code_Source
  Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache
  ☆13Updated 9 years ago
• pulp-platform / axi_llc
  ☆30Updated 2 weeks ago
• Aquaticfuller / OpenExSys_NoC
  OpenExSys_NoC a mesh-based network on chip IP.
  ☆15Updated last year
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 11 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆34Updated 7 months ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆51Updated 4 years ago
• rggen / rggen-sample-testbench
  ☆14Updated 2 months ago