bohanw / jpeg_comp_verilogLinks
JPEG Compression RTL implementation
☆11Updated 8 years ago
Alternatives and similar repositories for jpeg_comp_verilog
Users that are interested in jpeg_comp_verilog are comparing it to the libraries listed below
Sorting:
- ☆16Updated 6 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆14Updated 6 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- Generic AXI master stub☆19Updated 11 years ago
- RISC-V IOMMU in verilog☆18Updated 3 years ago
- ☆17Updated 10 years ago
- Simple demo showing how to use the ping pong FIFO☆15Updated 9 years ago
- Direct Access Memory for MPSoC☆13Updated 3 months ago
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆30Updated 9 years ago
- To design test bench of the APB protocol☆17Updated 4 years ago
- ☆13Updated 2 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- Network on Chip for MPSoC☆27Updated 3 months ago
- Verification IP for Watchdog☆11Updated 4 years ago
- ☆21Updated 5 years ago
- ☆30Updated 2 weeks ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆19Updated 4 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆16Updated last year
- ☆10Updated 3 years ago
- RISC-V instruction set extensions for SM4 block cipher☆20Updated 5 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆15Updated 5 months ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- AXI X-Bar☆19Updated 5 years ago