Alternatives and similar repositories for spicy

Users that are interested in spicy are comparing it to the libraries listed below

• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆50Updated 9 years ago
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆88Updated 3 years ago
• kkiningh / cs231n-project
  CNN accelerator
  ☆29Updated 8 years ago
• fpgasystems / ZipML-PYNQ
  Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.
  ☆55Updated 8 years ago
• FelixWinterstein / Vivado-KMeans
  Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs
  ☆49Updated 8 years ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆75Updated 10 years ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆128Updated 2 years ago
• DreamIP / haddoc2
  Caffe to VHDL
  ☆68Updated 5 years ago
• sheldonucr / ee260_lab
  EE 260 Winter 2017: Advanced VLSI Design
  ☆68Updated 9 years ago
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆28Updated 5 years ago
• Xilinx / PYNQ-Networking
  Networking Overlay on PYNQ
  ☆50Updated 6 years ago
• manish-kj / Posit-HDL-Arithmetic
  Universal number Posit HDL Arithmetic Architecture generator
  ☆69Updated 6 years ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆52Updated 6 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆52Updated 2 years ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆118Updated last week
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆74Updated last year
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆34Updated 7 years ago
• chenhaoc / cnnhwpe
  ☆66Updated 3 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆107Updated 7 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• lite-david / comet
  RISC-V ISA based 32-bit processor written in HLS
  ☆16Updated 6 years ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆32Updated 2 years ago
• wady101 / Embedded-System-Design-Flow-on-Zynq
  Updated version of the XUP Workshops
  ☆18Updated 7 years ago
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆92Updated last year
• benjmarshall / hlsclt
  A Vivado HLS Command Line Helper Tool
  ☆36Updated 4 years ago
• hlslibs / ac_math
  Algorithmic C Math Library
  ☆67Updated 3 weeks ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆69Updated 11 months ago
• khoapham / efcad
  ☆16Updated 6 years ago
• icgrp / prflow_nested_dfx
  Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)
  ☆15Updated last year
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆128Updated 3 years ago