isi-rcg / spicyLinks
Hot & Spicy tool suite
☆23Updated 3 years ago
Alternatives and similar repositories for spicy
Users that are interested in spicy are comparing it to the libraries listed below
Sorting:
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆38Updated 2 weeks ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated this week
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- Project repo for the POSH on-chip network generator☆46Updated 2 months ago
- Next generation CGRA generator☆111Updated last week
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- CNN accelerator☆27Updated 7 years ago
- ☆18Updated 7 years ago
- ☆58Updated 5 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- Tutorials on HLS Design☆51Updated 5 years ago
- Algorithmic C Machine Learning Library☆23Updated 5 months ago
- Caffe to VHDL☆67Updated 4 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆18Updated 9 years ago
- ☆29Updated 6 years ago
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)☆14Updated last year
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆40Updated 2 years ago
- ☆94Updated 11 months ago
- Algorithmic C Math Library☆62Updated 2 weeks ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago