Alternatives and similar repositories for A-Number-Theoretic-Transform-Accelerator-with-Two-Parallel-Simplified-Butterfly-Units

Users that are interested in A-Number-Theoretic-Transform-Accelerator-with-Two-Parallel-Simplified-Butterfly-Units are comparing it to the libraries listed below

• momalab / CoPHEE
  CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
  ☆36Updated last year
• KULeuven-COSIC / NTRU_NTT_HW
  ☆25Updated 4 years ago
• alibaba-damo-academy / damo_ctl_cham
  ☆27Updated 2 years ago
• MEEPproject / fpga_shell
  MEEP FPGA Shell project, currently supporting Alveos u280 and u55c
  ☆14Updated last year
• florianhirner / proteus
  ☆24Updated last year
• flokrieger / Aloha-HE
  ☆28Updated 5 months ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆42Updated 6 years ago
• kemalderya / pqc-param-ntt
  ☆27Updated 3 years ago
• raymondrc / FPGA_SM4
  FPGA implementation of Chinese SM4 encryption algorithm.
  ☆56Updated 7 years ago
• NikhilRout / NTT-FPGA
  Verilog Implementation of the Number Theoretic Transform (NTT) and its inverse operation (INTT) utilizing modulo arithmetic for lattice-b…
  ☆15Updated 2 months ago
• acmert / parametric-ntt
  Parametric NTT/INTT Hardware Generator
  ☆80Updated 4 years ago
• zslwyuan / Zynq_HLS_DDR_Dataflow_kernel_2mm
  This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…
  ☆20Updated 6 years ago
• raymondrc / FPGA-SM3-HASH
  Description of Chinese SM3 Hash algorithm with Verilog HDL
  ☆52Updated 7 years ago
• lajanugen / Modular-Exponentiation
  Verilog Implementation of modular exponentiation using Montgomery multiplication
  ☆37Updated 11 years ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆32Updated 2 years ago
• tom-urkin / AMBA
  AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog
  ☆17Updated 2 years ago
• chipsalliance / adams-bridge
  Post-Quantum Cryptography IP Core (Crystals-Dilithium)
  ☆43Updated last week
• KULeuven-MICAS / tinyvers
  TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.
  ☆23Updated 2 years ago
• acmert / kyber-polmul-hw
  Hardware implementation of polynomial multiplication operation of CRYSTALS-KYBER PQC scheme
  ☆40Updated 4 years ago
• Csuk0914 / dnn-rtl
  Verilog RTL Implementation of DNN
  ☆10Updated 7 years ago
• gilani / fpfma
  Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)
  ☆22Updated 12 years ago
• brigio345 / DaCH
  DaCH: dataflow cache for high-level synthesis.
  ☆20Updated 2 years ago
• mcjtag / bitonic_sorter
  Bitonic sorter (Batcher's sorting network) written in Verilog.
  ☆37Updated last year
• sjj-star / automatically-generate-Wallace-Tree-VerilogHDL-code
  本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。
  ☆27Updated 2 years ago
• xiang-rc / cfntt_ref
  ☆36Updated last year
• tharunchitipolu / Dadda-Multiplier-using-CSA
  Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
  ☆39Updated last year
• hyoukjun / microswitch-noc
  ☆29Updated 6 years ago
• GJigar / ZYNQ_CNN
  ☆19Updated 3 years ago
• fatestudio / RSA4096_NEW
  ☆13Updated 10 years ago
• lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS
  This project implements a convolution kernel based on vivado HLS on zcu104
  ☆36Updated 5 years ago