XBQ314 / A-Number-Theoretic-Transform-Accelerator-with-Two-Parallel-Simplified-Butterfly-Units
Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现,基为2,有两个并行的蝶形单元
☆14Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for A-Number-Theoretic-Transform-Accelerator-with-Two-Parallel-Simplified-Butterfly-Units
- Parametric NTT/INTT Hardware Generator☆59Updated 3 years ago
- ☆13Updated 2 months ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆27Updated 8 months ago
- ☆24Updated 3 months ago
- processor for post-quantum cryptography☆14Updated 4 years ago
- ☆22Updated 4 years ago
- ☆17Updated 2 years ago
- Verilog Implementation of modular exponentiation using Montgomery multiplication☆32Updated 10 years ago
- Description of Chinese SM3 Hash algorithm with Verilog HDL☆45Updated 6 years ago
- eyeriss-chisel3☆38Updated 2 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆9Updated 4 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆12Updated 4 months ago
- MulApprox - A comprehensive library of state-of-the-art approximate multipliers☆19Updated 3 years ago
- ☆20Updated last year
- 3×3脉动阵列乘法器☆34Updated 5 years ago
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆29Updated 6 years ago
- ☆22Updated 5 years ago
- FFT generator using Chisel☆56Updated 3 years ago
- Hardware implementation of polynomial multiplication operation of CRYSTALS-KYBER PQC scheme☆25Updated 2 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆70Updated 5 years ago
- A verilog implementation for Network-on-Chip☆66Updated 6 years ago
- Acceleration of TFHE-based Homomorphic NAND Gate on FPGA☆14Updated 3 years ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆45Updated 6 years ago
- ☆19Updated 10 months ago
- Single Long Short Term Memory (LSTM) cell : Verilog Implementation☆29Updated 4 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆19Updated 3 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆34Updated 5 months ago
- ☆66Updated 10 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- CNN accelerator using NoC architecture☆15Updated 5 years ago