XBQ314 / A-Number-Theoretic-Transform-Accelerator-with-Two-Parallel-Simplified-Butterfly-UnitsLinks
Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现，基为2，有两个并行的蝶形单元
☆19Updated 2 years ago
Alternatives and similar repositories for A-Number-Theoretic-Transform-Accelerator-with-Two-Parallel-Simplified-Butterfly-Units
Users that are interested in A-Number-Theoretic-Transform-Accelerator-with-Two-Parallel-Simplified-Butterfly-Units are comparing it to the libraries listed below
Sorting:
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆33Updated last year
- ☆24Updated 4 years ago
- ☆26Updated 2 years ago
- MEEP FPGA Shell project, currently supporting Alveos u280 and u55c☆14Updated last year
- ☆20Updated last year
- ☆26Updated 2 weeks ago
- Parametric NTT/INTT Hardware Generator☆73Updated 4 years ago
- Description of Chinese SM3 Hash algorithm with Verilog HDL☆50Updated 7 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆39Updated 5 years ago
- ☆36Updated last year
- FPGA implementation of Chinese SM4 encryption algorithm.☆55Updated 7 years ago
- Bitonic sorter (Batcher's sorting network) written in Verilog.☆34Updated 10 months ago
- Verilog Implementation of modular exponentiation using Montgomery multiplication☆34Updated 10 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆19Updated 2 years ago
- Verilog RTL Implementation of DNN☆10Updated 7 years ago
- ☆24Updated 3 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆21Updated 6 years ago
- ☆26Updated 4 years ago
- ☆19Updated 2 years ago
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆19Updated 2 weeks ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆26Updated 2 years ago
- ☆27Updated 5 years ago
- ☆13Updated 10 years ago
- DMA controller for CNN accelerator☆14Updated 8 years ago
- Acceleration of TFHE-based Homomorphic NAND Gate on FPGA☆17Updated 4 years ago
- EE 272B - VLSI Design Project☆13Updated 4 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 5 years ago
- RISC-V instruction set extensions for SM4 block cipher☆20Updated 5 years ago
- ☆13Updated 6 years ago