XBQ314 / A-Number-Theoretic-Transform-Accelerator-with-Two-Parallel-Simplified-Butterfly-UnitsLinks
Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现,基为2,有两个并行的蝶形单元
☆19Updated 3 years ago
Alternatives and similar repositories for A-Number-Theoretic-Transform-Accelerator-with-Two-Parallel-Simplified-Butterfly-Units
Users that are interested in A-Number-Theoretic-Transform-Accelerator-with-Two-Parallel-Simplified-Butterfly-Units are comparing it to the libraries listed below
Sorting:
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Updated last year
- ☆26Updated 2 years ago
- ☆25Updated 4 years ago
- ☆23Updated last year
- ☆28Updated 4 months ago
- Parametric NTT/INTT Hardware Generator☆78Updated 4 years ago
- MEEP FPGA Shell project, currently supporting Alveos u280 and u55c☆14Updated last year
- Bitonic sorter (Batcher's sorting network) written in Verilog.☆35Updated last year
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆41Updated 6 years ago
- Description of Chinese SM3 Hash algorithm with Verilog HDL☆51Updated 7 years ago
- FFT generator using Chisel☆62Updated 4 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆27Updated 2 years ago
- Verilog Implementation of the Number Theoretic Transform (NTT) and its inverse operation (INTT) utilizing modulo arithmetic for lattice-b…☆14Updated last month
- The Verilog source code for DRUM approximate multiplier.☆32Updated 2 years ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆56Updated 7 years ago
- ☆26Updated 5 years ago
- ☆25Updated 3 years ago
- Verilog Implementation of modular exponentiation using Montgomery multiplication☆36Updated 11 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆20Updated 6 years ago
- Implement a bitonic sorting network on FPGA☆46Updated 4 years ago
- processor for post-quantum cryptography☆17Updated 5 years ago
- ☆36Updated last year
- Verilog Implementation of 32-bit Floating Point Adder☆44Updated 5 years ago
- Verilog program☆16Updated 5 years ago
- DaCH: dataflow cache for high-level synthesis.☆20Updated 2 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆23Updated 2 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- ☆15Updated 6 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- eyeriss-chisel3☆40Updated 3 years ago