Alternatives and similar repositories for Hamming-ECC:

Users that are interested in Hamming-ECC are comparing it to the libraries listed below

• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆56Updated 4 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆38Updated 11 months ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆36Updated 3 years ago
• oprecomp / DDR4_controller
  ☆54Updated 4 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆28Updated this week
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆21Updated 6 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 4 years ago
• freecores / ddr3_sdram
  DDR3 SDRAM controller
  ☆18Updated 10 years ago
• pulp-platform / axi_spi_slave
  ☆25Updated 3 years ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆45Updated 5 months ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆26Updated 2 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆60Updated 3 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆42Updated 4 years ago
• freecores / xge_mac
  Ethernet 10GE MAC
  ☆45Updated 10 years ago
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆38Updated 10 years ago
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆23Updated 2 months ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆18Updated 2 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆54Updated 2 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 11 months ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 4 years ago
• pulp-platform / axi2apb
  ☆20Updated 5 years ago
• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• pulp-platform / axi_llc
  ☆25Updated this week
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆48Updated 3 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• freecores / jtag
  JTAG Test Access Port (TAP)
  ☆33Updated 10 years ago