Hamming ECC Encoder and Decoder to protect memories
☆35Jan 28, 2025Updated last year
Alternatives and similar repositories for Hamming-ECC
Users that are interested in Hamming-ECC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆21Oct 31, 2017Updated 8 years ago
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Dec 14, 2019Updated 6 years ago
- USB capture IP☆25Jun 6, 2020Updated 5 years ago
- AES☆15Oct 4, 2022Updated 3 years ago
- Verification of Ethernet Switch System Verilog☆12Oct 21, 2016Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆55Dec 6, 2023Updated 2 years ago
- An FPGA-accelerated platform for FEC analysis of wireline systems☆12Jan 21, 2025Updated last year
- AHB DMA 32 / 64 bits☆61Jul 17, 2014Updated 11 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆82Apr 28, 2023Updated 3 years ago
- Verilog based BCH encoder/decoder☆132Sep 26, 2022Updated 3 years ago
- 基于arm cortex-m0内核的xillinx fpga sopc工程项目☆13May 28, 2019Updated 6 years ago
- Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…☆55Apr 29, 2015Updated 11 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Aug 8, 2017Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An implementation of the decoding of BCH codes resistant to timing attacks☆11Sep 18, 2020Updated 5 years ago
- minimal code to access ps DDR from PL☆22Oct 18, 2019Updated 6 years ago
- How to use the Intel JTAG primitive without using virtual JTAG☆17Oct 31, 2021Updated 4 years ago
- ☆48Updated this week
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆30Aug 16, 2021Updated 4 years ago
- 给定ARM Cortex-M3的软核，扩展周围的AMBA总线以及基本外设，完成在上面的汇编以及C语言的执行☆19Aug 26, 2019Updated 6 years ago
- An Ethernet MAC conforming to IEEE 802.3☆24May 13, 2017Updated 8 years ago
- Educational 16-bit MIPS Processor☆18Feb 16, 2019Updated 7 years ago
- unsigned Radix-2 SRT division,基2除法☆16May 12, 2015Updated 10 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆73Dec 17, 2025Updated 4 months ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆243Jul 16, 2023Updated 2 years ago
- 国科大软件安全原理作业☆25Oct 27, 2020Updated 5 years ago
- ☆30Jul 9, 2025Updated 9 months ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- Huffman encoder☆10Sep 8, 2013Updated 12 years ago
- ☆10Nov 8, 2019Updated 6 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Jan 17, 2026Updated 3 months ago
- GCC toolchain for MSP430☆10Apr 2, 2019Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- MMC (and derivative standards) host controller☆25Sep 14, 2020Updated 5 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆82Dec 1, 2022Updated 3 years ago
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆20Apr 19, 2026Updated 2 weeks ago
- AMBA bus generator including AXI, AHB, and APB☆122Jul 29, 2021Updated 4 years ago
- HARV - HArdened Risc-V☆16Mar 10, 2022Updated 4 years ago
- A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.☆14Nov 23, 2022Updated 3 years ago
- Next186 SoC PC☆17Feb 5, 2014Updated 12 years ago