RoaLogic / Hamming-ECC
Hamming ECC Encoder and Decoder to protect memories
☆31Updated last month
Alternatives and similar repositories for Hamming-ECC:
Users that are interested in Hamming-ECC are comparing it to the libraries listed below
- Generic FIFO implementation with optional FWFT☆55Updated 4 years ago
- Platform Level Interrupt Controller☆37Updated 10 months ago
- USB -> AXI Debug Bridge☆36Updated 3 years ago
- ☆53Updated 4 years ago
- Extensible FPGA control platform☆59Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- ☆25Updated 3 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆28Updated last month
- Open FPGA Modules☆23Updated 5 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- UART models for cocotb☆26Updated 2 years ago
- ☆21Updated last week
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆19Updated 4 months ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated last month
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆66Updated 2 years ago
- DMA Hardware Description with Verilog☆13Updated 5 years ago
- ☆19Updated 5 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 8 years ago
- JTAG Test Access Port (TAP)☆33Updated 10 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago