UART in Verilog and VHDL
☆18Aug 21, 2022Updated 3 years ago
Alternatives and similar repositories for UART
Users that are interested in UART are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Single Port RAM, Dual Port RAM, FIFO☆33May 17, 2022Updated 3 years ago
- SPI Slave for FPGA in Verilog and VHDL☆229May 11, 2024Updated last year
- SPI Master for FPGA - VHDL and Verilog☆333Aug 22, 2023Updated 2 years ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆12May 2, 2022Updated 3 years ago
- ☆14Jan 23, 2024Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- DSP University Project - Matlab, Simulations, and Verilog Files☆14Jan 14, 2020Updated 6 years ago
- RTL code of some arbitration algorithm☆16Aug 25, 2019Updated 6 years ago
- Verilog UART FIFO that will just echo back characters. Useful for testing the communications path.☆13May 5, 2015Updated 10 years ago
- Go Board FPGA Project for Ambient Light Sensor in VHDL and Verilog☆10Apr 20, 2019Updated 6 years ago
- NiMUD: Shared Adventure Game brought to you by Locke; NiM5 is an advanced multi-user gaming server.☆11Sep 4, 2024Updated last year
- A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.☆17May 30, 2023Updated 2 years ago
- Integrated Circuit Design - IC Design Flow and Project-Based Learning☆50Mar 1, 2026Updated 3 weeks ago
- 16QAM modulation and demodulation by Verilog☆22Jan 4, 2021Updated 5 years ago
- Vitis-AI 1.3 TensorFlow2 flow with a custom CNN model, targeted ZCU102 evaluation board.☆15Apr 6, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆21Nov 26, 2018Updated 7 years ago
- Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout☆14May 11, 2014Updated 11 years ago
- How to connect an USB Keyboard / Mouse to a embedded system with a CH9350 Chip☆25Sep 30, 2022Updated 3 years ago
- ☆11Sep 23, 2023Updated 2 years ago
- Vitis HLS 2022.2 projects source code: C design, C simulation, RTL simulation.【vitis_hls工程】☆23Jun 9, 2025Updated 9 months ago
- This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs …☆18Apr 20, 2019Updated 6 years ago
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆15Sep 12, 2023Updated 2 years ago
- This project discusses the design procedure of a Low Dropout Voltage Regulator (LDO) circuit.☆21Feb 28, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- 通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结☆24Nov 8, 2019Updated 6 years ago
- An adapter board with pin headers for low-pin count (LPC) FPGA Mezzanine Cards (FMC).☆11Nov 2, 2020Updated 5 years ago
- Ultralightweight JSON parser in ANSI C☆10Mar 8, 2017Updated 9 years ago
- 基于开源库libyuv 实现NV21转I420、I420转NV21 以及对I420数据进行裁剪、缩放、旋转、镜像等操作☆10Jul 16, 2020Updated 5 years ago
- A simple 8 bit UART implementation in Verilog, with tests and timing diagrams☆41Oct 3, 2025Updated 5 months ago
- Emulating Quantum Circuits on FPGAs☆28Nov 22, 2023Updated 2 years ago
- Schematic, Layout Design & Simulation in 180nm Technology☆22Nov 21, 2020Updated 5 years ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆24May 2, 2025Updated 10 months ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆18Jan 27, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆31Dec 31, 2022Updated 3 years ago
- We live in a colorful world, but how much do you really know about color? You eyes may deceive you, while the sensors don’t lie. This AS7…☆12Jan 20, 2022Updated 4 years ago
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- Репозиторий факультатива по функциональной верификации НИУ МИЭТ☆16Aug 24, 2024Updated last year
- Учебные материалы Альянса RISC-V☆16Jun 30, 2025Updated 8 months ago
- GPU monitor for CUDA devices☆14Mar 3, 2013Updated 13 years ago
- All the information and scripts used to setup a new cross platform development environment☆31Mar 2, 2020Updated 6 years ago