yucanliu / VLSI_SNNLinks
A Spiking Neuron Network Project in Verilog Implementation
☆25Updated 7 years ago
Alternatives and similar repositories for VLSI_SNN
Users that are interested in VLSI_SNN are comparing it to the libraries listed below
Sorting:
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆19Updated 5 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆60Updated 8 months ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆74Updated 2 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆36Updated 6 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆37Updated 3 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆38Updated 6 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆25Updated 5 years ago
- ☆19Updated 2 weeks ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆35Updated 5 years ago
- ☆20Updated 4 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆15Updated 2 years ago
- A repository FPGA-friendly SNN models☆35Updated 4 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆33Updated last year
- ☆37Updated 6 years ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆14Updated 2 years ago
- Spiking Neural Network Accelerator☆15Updated 3 years ago
- ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.☆207Updated 6 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆24Updated last year
- Spiking Neural Network RTL Implementation☆62Updated 4 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆38Updated last year
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆17Updated 2 years ago
- A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated …☆61Updated last year
- ☆28Updated 3 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆107Updated 5 years ago
- ☆16Updated last year
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆30Updated 2 months ago