m-spr / RCEHDCLinks
An automated HDC platform
☆10Updated 4 months ago
Alternatives and similar repositories for RCEHDC
Users that are interested in RCEHDC are comparing it to the libraries listed below
Sorting:
- Efficient single-pass hyperdimensional classifier. Mirror of https://gitlab.com/biaslab/onlinehd☆9Updated 4 years ago
- bitfusion verilog implementation☆10Updated 3 years ago
- Resource Utilization and Latency Estimation for ML on FPGA.☆15Updated last week
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆12Updated 4 years ago
- FPGA Implementation of Image Processing for MNIST Dataset Based on Convolutional Neural Network Algorithm (CNN)☆11Updated last year
- ☆11Updated 5 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated 2 years ago
- ☆19Updated 4 years ago
- SNN on FPGA☆10Updated 3 years ago
- Framework for radix encoded SNN on FPGA☆14Updated 3 years ago
- LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks, MICRO 2024.☆11Updated 4 months ago
- Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"☆11Updated 2 years ago
- EE 272B - VLSI Design Project☆12Updated 4 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 6 years ago
- ☆10Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- Fully Hardware-Based Stochastic Neural Network☆22Updated 6 months ago
- A Custom RISC-V Instruction Extension for SNN and CNN Computation☆16Updated 11 months ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆19Updated 11 months ago
- A nest brain simulator based on FPGA(LIF NEURON)☆14Updated 3 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆34Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆37Updated last year
- ☆12Updated 7 years ago
- ☆11Updated 2 years ago
- ☆14Updated 3 years ago
- ☆27Updated 3 months ago
- Collection of kernel accelerators optimised for LLM execution☆19Updated 3 months ago
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆16Updated 3 years ago
- MINT, Multiplier-less INTeger Quantization for Energy Efficient Spiking Neural Networks, ASP-DAC 2024, Nominated for Best Paper Award☆15Updated last year