Alternatives and similar repositories for RCEHDC

Users that are interested in RCEHDC are comparing it to the libraries listed below

• mean9park / BitFusion-verilog
  bitfusion verilog implementation
  ☆12Updated 3 years ago
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆12Updated 4 years ago
• sweetwenwen / Stochastic-computing-based-neural-network-accelerator
  ☆11Updated 5 years ago
• snagiri / CSE237D-PYNQ-SNN-Accelerator
  Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board
  ☆37Updated 6 years ago
• arkhodamoradi / s2n2
  ☆17Updated 4 years ago
• oshears / SNN-FPGA-Implementation
  ☆19Updated 4 years ago
• SivannaKing / SEU-ASIC-IOT-ECGAI
  Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators
  ☆16Updated 2 years ago
• Minz9 / SNN-on-FPGA
  SNN on FPGA
  ☆10Updated 3 years ago
• hyupupup / conv_systolic_array
  (Verilog) A simple convolution layer implementation with systolic array structure
  ☆12Updated 3 years ago
• saunak1994 / CyNAPSEv11
  The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL
  ☆34Updated 5 years ago
• XAli-SHX / FPGA-Implementation-of-Image-Processing-for-MNIST-Dataset-Based-on-CNN-Algorithm
  FPGA Implementation of Image Processing for MNIST Dataset Based on Convolutional Neural Network Algorithm (CNN)
  ☆11Updated last year
• Mattjesc / Efficient-FPGA-CNN-Accelerator
  Efficient FPGA-Based Accelerator for Convolutional Neural Networks
  ☆23Updated last year
• Intelligent-Microsystems-Lab / SNNQuantPrune
  Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"
  ☆11Updated 2 years ago
• HanPU-Code / CNN_YOLO_AI_accelerator
  This project is to design yolo AI accelerator in verilog HDL.
  ☆22Updated 10 months ago
• eda-lab / CNNAF-CNN-Accelerator
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆10Updated 3 years ago
• BaoBao-zhu / RV-SCNN
  A Custom RISC-V Instruction Extension for SNN and CNN Computation
  ☆18Updated last year
• Zhu-Zixuan / Bitlet-PE
  A bit-level sparsity-awared multiply-accumulate process element.
  ☆16Updated last year
• DanielGerlinghoff / radix-encoding
  Framework for radix encoded SNN on FPGA
  ☆14Updated 3 years ago
• hsieh672 / SNN-Accelerator
  A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…
  ☆14Updated last year
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆39Updated last year
• puccinic / Transformer_dataflow
  C++ code for HLS FPGA implementation of transformer
  ☆17Updated 11 months ago
• cceroici / Stochastic-Neural-Network
  Fully Hardware-Based Stochastic Neural Network
  ☆22Updated 7 months ago
• sjduan / LeHDC
  ☆14Updated 5 months ago
• neurosim / DNN_NeuroSim_V2.0
  Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)
  ☆52Updated 4 years ago
• booniebears / CoMN
  ☆18Updated last year
• ECASLab / hls-fpga-accelerators
  Collection of kernel accelerators optimised for LLM execution
  ☆19Updated 5 months ago
• Deepak42074 / SRAM_IMC_MPW8
  The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…
  ☆13Updated 2 years ago
• eldrickm / wakey_wakey
  EE 272B - VLSI Design Project
  ☆13Updated 4 years ago
• fabio-montagna / PULP-HD
  ☆13Updated 7 years ago
• RuokaiYin / LoAS
  LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks, MICRO 2024.
  ☆12Updated 5 months ago