m-spr / RCEHDC
An automated HDC platform
☆9Updated last month
Alternatives and similar repositories for RCEHDC
Users that are interested in RCEHDC are comparing it to the libraries listed below
Sorting:
- A Custom RISC-V Instruction Extension for SNN and CNN Computation☆14Updated 8 months ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated last year
- Efficient single-pass hyperdimensional classifier. Mirror of https://gitlab.com/biaslab/onlinehd☆9Updated 4 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- Resource Utilization and Latency Estimation for ML on FPGA.☆10Updated this week
- ☆11Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- ☆18Updated 4 years ago
- ☆17Updated 4 years ago
- Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"☆11Updated 2 years ago
- LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks, MICRO 2024.☆10Updated last month
- (Verilog) A simple convolution layer implementation with systolic array structure☆12Updated 3 years ago
- A heterogeneous accelerator-centric compute cluster☆15Updated this week
- MINT, Multiplier-less INTeger Quantization for Energy Efficient Spiking Neural Networks, ASP-DAC 2024, Nominated for Best Paper Award☆13Updated last year
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆15Updated 2 years ago
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆7Updated last year
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆34Updated last year
- Framework for radix encoded SNN on FPGA☆12Updated 3 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆15Updated 10 months ago
- Hardware and software implementation of Sparsely-active SNNs☆14Updated 4 months ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆11Updated 9 months ago
- EE 272B - VLSI Design Project☆11Updated 3 years ago
- Fully Hardware-Based Stochastic Neural Network☆21Updated 3 months ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆12Updated last year
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆33Updated 5 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 5 years ago
- A neural network built in Verilog for the DE1-SoC FPGA board for handwritten digit recognition.☆17Updated 5 years ago
- ☆10Updated 6 years ago
- A nest brain simulator based on FPGA(LIF NEURON)☆14Updated 3 years ago
- ☆15Updated last year