thesrsakabuvttchi / VLIWLinks
This is a simple VLIW based processor written in Verilog. A Python script has also been included to simulate static instruction scheduling.
☆17Updated 4 years ago
Alternatives and similar repositories for VLIW
Users that are interested in VLIW are comparing it to the libraries listed below
Sorting:
- HLS for Networks-on-Chip☆36Updated 4 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆15Updated 7 months ago
- ☆16Updated 5 years ago
- ☆78Updated 11 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- ☆30Updated 5 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆15Updated last year
- ☆15Updated 3 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆26Updated 2 years ago
- ☆14Updated 2 years ago
- Ratatoskr NoC Simulator☆28Updated 4 years ago
- ☆56Updated 6 years ago
- Development of a Network on Chip Simulation using SystemC.☆34Updated 8 years ago
- ☆67Updated 4 years ago
- ☆27Updated 6 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆14Updated 3 years ago
- A repository for SystemC Learning examples☆71Updated 3 years ago
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- NVDLA small config implementation on Zynq ZCU104 (evaluation)☆24Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Updated 6 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0☆26Updated 2 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆82Updated 2 years ago
- ☆64Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated this week
- Tutorials on HLS Design☆52Updated 5 years ago
- Design and UVM-TB of RISC -V Microprocessor☆28Updated last year
- Xilinx AXI VIP example of use☆42Updated 4 years ago