AakashKT / CuckooHashingHLSLinks
HLS implementation of cuckoo hashing. Refer to paper : https://ieeexplore.ieee.org/document/7577355/
☆14Updated 6 years ago
Alternatives and similar repositories for CuckooHashingHLS
Users that are interested in CuckooHashingHLS are comparing it to the libraries listed below
Sorting:
- Networking Template Library for Vivado HLS☆28Updated 4 years ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆36Updated 2 years ago
- Network packet parser generator☆51Updated 4 years ago
- An FPGA-based NetTLP adapter☆26Updated 5 years ago
- DPDK Drivers for AMD OpenNIC☆25Updated last year
- A platform for emulating Virtio devices with FPGAs☆26Updated 4 years ago
- Verilog PCI express components☆22Updated last year
- pcie-bench code for NetFPGA/VCU709 cards☆37Updated 6 years ago
- A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark☆48Updated 3 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆47Updated 4 years ago
- Virtio implementation in SystemVerilog☆47Updated 7 years ago
- SmartNIC☆14Updated 6 years ago
- ☆46Updated 5 years ago
- Virtio front-end and back-end bridge, implemented with FPGA.☆28Updated 4 years ago
- PCIe DMA Subsystem based on Xilinx XAPP1171☆46Updated last year
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- Caribou: Distributed Smart Storage built with FPGAs☆66Updated 6 years ago
- Open source FPGA-based NIC and platform for in-network compute☆63Updated 7 months ago
- P4-14/16 Bluespec Compiler☆86Updated 7 years ago
- ☆32Updated 9 years ago
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆20Updated 2 years ago
- ☆34Updated 2 years ago
- Ethernet switch implementation written in Verilog☆47Updated last year
- P4 compatible HLS modules☆11Updated 7 years ago
- ☆21Updated 6 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆17Updated 5 years ago
- ☆16Updated 3 years ago
- Simple hash table on Verilog (SystemVerilog)☆49Updated 9 years ago
- OmniXtend cache coherence protocol☆82Updated 4 years ago
- ☆62Updated 3 months ago