Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design contest.
☆115Jun 27, 2018Updated 8 years ago
Alternatives and similar repositories for Deploying_CNN_on_FPGA_using_OpenCL
Users that are interested in Deploying_CNN_on_FPGA_using_OpenCL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.☆82Oct 3, 2023Updated 2 years ago
- DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel…☆96Nov 7, 2020Updated 5 years ago
- An OpenCL-based FPGA Accelerator for Convolutional Neural Networks☆1,388Feb 14, 2022Updated 4 years ago
- A crypto accelerator written for HLS to an FPGA that actually makes it slower than running it on your computer☆19Dec 11, 2018Updated 7 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆38May 27, 2021Updated 5 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆14Feb 7, 2020Updated 6 years ago
- FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.☆187Jan 28, 2017Updated 9 years ago
- This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.☆794Dec 10, 2019Updated 6 years ago
- FreeRTOS with LwIP integration in the Nios II EDS☆20Jan 30, 2016Updated 10 years ago
- ☆69May 6, 2020Updated 6 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆33May 30, 2019Updated 7 years ago
- ☆24Oct 7, 2021Updated 4 years ago
- FPGA Accelerator for CNN using Vivado HLS☆340Oct 25, 2021Updated 4 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆13May 14, 2019Updated 7 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- 🤖 SoCFPGA: Open-Source Embedded Linux Distribution with a highly flexible build system, developed for Intel (ALTERA) SoC-FPGAs (Cyclone …☆121Oct 18, 2021Updated 4 years ago
- C++ RTL simulator for EIE(https://arxiv.org/abs/1602.01528)☆25Mar 17, 2021Updated 5 years ago
- A novel FPGA-based intent recognition systemutilizing deep recurrent neural networks☆26Aug 25, 2021Updated 5 years ago
- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators☆10Sep 7, 2015Updated 11 years ago
- ☆18Feb 13, 2021Updated 5 years ago
- ☆32Apr 21, 2019Updated 7 years ago
- Processor-FPGA transfer rate measurements in CycloneV-SoC☆15Nov 23, 2018Updated 7 years ago
- My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket☆30Jul 31, 2019Updated 7 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Feb 17, 2021Updated 5 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- FPGArduino binary☆13Aug 5, 2019Updated 7 years ago
- CK workflow, portable packages and other artifacts for the ReQuEST-ASPLOS'18 submission:☆12Jan 16, 2019Updated 7 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆342Jan 20, 2025Updated last year
- Chinese Guide for Alveo Getting Started☆13May 18, 2020Updated 6 years ago
- NVDLA small config implementation on Zynq ZCU104 (evaluation)☆24Mar 25, 2019Updated 7 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆36Mar 15, 2020Updated 6 years ago
- Deep Neural Network inference using Xilinx Zynq-7000 chip.☆29Jun 26, 2020Updated 6 years ago
- RTL implementation of Flex-DPE.☆119Feb 22, 2020Updated 6 years ago
- Design and verification of a simple pipelined RISC processor in Verilog, featuring a five-stage pipeline and custom ISA.☆16Jul 15, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This project implemented an unoptimized simple convolutional neural network in ZYNQ's PL and realized data transmission through axidma dr…☆12Aug 5, 2018Updated 8 years ago
- Synthetic Traffic Models Capturing a Full Range of Cache Coherent Behaviour☆15May 17, 2019Updated 7 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆163Feb 11, 2025Updated last year
- Hardware Accelerators on FPGA for Computer Vision Applications☆16Dec 16, 2025Updated 9 months ago
- A hardware accelerator for General Matrix Multiply, developed in SystemC using ESP.☆20May 26, 2021Updated 5 years ago
- Hybrid BFS on Xilinx Zynq☆18Jun 9, 2015Updated 11 years ago
- Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2☆19Apr 11, 2020Updated 6 years ago