Er1cZ / Deploying_CNN_on_FPGA_using_OpenCLLinks
Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design contest.
☆112Updated 7 years ago
Alternatives and similar repositories for Deploying_CNN_on_FPGA_using_OpenCL
Users that are interested in Deploying_CNN_on_FPGA_using_OpenCL are comparing it to the libraries listed below
Sorting:
- OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.☆80Updated 2 years ago
- DPU on PYNQ☆231Updated 3 months ago
- Vitis HLS Library for FINN☆209Updated last month
- Convolutional Neural Network Using High Level Synthesis☆89Updated 5 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆161Updated 6 years ago
- This project is trying to create a base vitis platform to run with DPU☆48Updated 5 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆47Updated 5 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- A convolutional neural network implemented in hardware (verilog)☆164Updated 8 years ago
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆265Updated 2 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆155Updated 8 months ago
- IC implementation of TPU☆134Updated 5 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆233Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆174Updated 5 years ago
- ☆48Updated 7 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆195Updated 7 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107Updated 7 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆204Updated 5 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- PYNQ, Neural network Language model, Overlay☆111Updated 6 years ago
- ☆117Updated 4 years ago
- hls code zynq 7020 pynq z2 CNN☆88Updated 6 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆112Updated 5 years ago
- AMD University Program HLS tutorial☆118Updated last year
- ☆90Updated 5 years ago
- FPGA/AES/LeNet/VGG16☆109Updated 7 years ago
- NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…☆231Updated 6 years ago
- SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials☆155Updated 5 years ago