artecs-group / RVfpga-sim-addons
Recent updates and features added to the RVfpga course developed by Imagination Technologies.
☆14Updated this week
Alternatives and similar repositories for RVfpga-sim-addons:
Users that are interested in RVfpga-sim-addons are comparing it to the libraries listed below
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 2 months ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated last year
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆24Updated this week
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- Open Source PHY v2☆27Updated 11 months ago
- Open FPGA Modules☆23Updated 6 months ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 2 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Reconfigurable Binary Engine☆16Updated 4 years ago
- Platform Level Interrupt Controller☆40Updated 11 months ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- Wraps the NVDLA project for Chipyard integration☆19Updated 2 weeks ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆51Updated 3 months ago
- ☆36Updated 2 years ago
- RISC-V Nox core☆62Updated last month
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆34Updated last month
- ☆26Updated 4 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Updated 3 weeks ago
- A simple, scalable, source-synchronous, all-digital DDR link☆24Updated 2 months ago
- Implementation of post-process coverage, and batch waveform search☆15Updated 3 years ago
- ☆59Updated 3 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆27Updated 6 months ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year