artecs-group / RVfpga-sim-addonsLinks
Recent updates and additions on teaching experiences, papers, talks, and tools related to the RVfpga course developed by Imagination Technologies.
☆17Updated this week
Alternatives and similar repositories for RVfpga-sim-addons
Users that are interested in RVfpga-sim-addons are comparing it to the libraries listed below
Sorting:
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 5 months ago
- ☆59Updated 3 years ago
- Wraps the NVDLA project for Chipyard integration☆21Updated 3 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 3 weeks ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- CMake based hardware build system☆29Updated 2 weeks ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆62Updated 5 months ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆26Updated 3 weeks ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆90Updated 6 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 8 months ago
- Open source ISS and logic RISC-V 32 bit project☆54Updated last month
- Open Source PHY v2☆29Updated last year
- Solving Sudokus using open source formal verification tools☆17Updated 2 years ago
- ☆17Updated this week
- ☆68Updated this week
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Algorithmic C Machine Learning Library☆25Updated 7 months ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- ☆33Updated 2 years ago
- ☆27Updated last week
- ☆39Updated last year
- SystemVerilog RTL Linter for YoSys☆21Updated 7 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆29Updated last month
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- Reconfigurable Binary Engine☆17Updated 4 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆34Updated 2 years ago
- Demo SoC for SiliconCompiler.☆59Updated last month
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago