Alternatives and similar repositories for RVfpga-sim-addons

Users that are interested in RVfpga-sim-addons are comparing it to the libraries listed below

• SameLight / ITRI-OpenDLA
  Express DLA implementation for FPGA, revised based on NVDLA.
  ☆11Updated 6 years ago
• pulp-platform / rbe
  Reconfigurable Binary Engine
  ☆17Updated 4 years ago
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆26Updated 10 months ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆52Updated 5 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆67Updated last month
• adki / RTL-Design-For-FPGA
  Engineering Program on RTL Design for FPGA Accelerator
  ☆31Updated 5 years ago
• learn-cocotb / tutorial
  Complete tutorial code.
  ☆21Updated last year
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆61Updated 2 weeks ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆67Updated 8 months ago
• pulp-platform / neureka
  2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
  ☆27Updated 2 weeks ago
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆65Updated 11 months ago
• verilator / example-systemverilog
  ☆40Updated last year
• hossein1387 / BARVINN
  BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
  ☆91Updated 9 months ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆31Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 3 months ago
• Muriukidavid / systemc-examples
  A repository for SystemC Learning examples
  ☆71Updated 3 years ago
• arm-university / System-on-Chip-Design-with-Arm-Cortex-M-Processors
  A reference book on System-on-Chip Design
  ☆36Updated 4 months ago
• pulp-platform / redmule
  ☆80Updated last week
• pulp-platform / uvm-components
  Contains commonly used UVM components (agents, environments and tests).
  ☆30Updated 7 years ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 4 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 4 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆72Updated 10 months ago
• hossein1387 / pito_riscv
  A Barrel design of RV32I
  ☆22Updated 2 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• aignacio / nox
  RISC-V Nox core
  ☆68Updated 3 months ago
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆20Updated 2 years ago
• chipsalliance / Cores-SweRV-Support-Package
  Processor support packages
  ☆19Updated 4 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 3 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆61Updated last year
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆22Updated 4 years ago