artecs-group / RVfpga-sim-addonsLinks
Links to the RVfpga materials developed by Imagination Technologies, and recent additions on teaching materials and experiences, papers, talks, and tools.
☆18Updated this week
Alternatives and similar repositories for RVfpga-sim-addons
Users that are interested in RVfpga-sim-addons are comparing it to the libraries listed below
Sorting:
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆75Updated last month
- Open Source PHY v2☆29Updated last year
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Algorithmic C Machine Learning Library☆26Updated 8 months ago
- Tutorials on HLS Design☆52Updated 5 years ago
- ☆40Updated last year
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Updated 2 years ago
- Complete tutorial code.☆21Updated last year
- EE 260 Winter 2017: Advanced VLSI Design☆66Updated 8 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆63Updated 9 months ago
- Open source ISS and logic RISC-V 32 bit project☆57Updated 2 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 4 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆96Updated 2 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆65Updated 7 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆48Updated 4 years ago
- Contains commonly used UVM components (agents, environments and tests).☆30Updated 7 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆20Updated 2 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated last week
- ☆42Updated 3 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 6 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆120Updated last month
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆90Updated 8 months ago
- ☆60Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 months ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆29Updated 5 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆69Updated 8 months ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆65Updated last month
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 3 months ago
- SystemVerilog modules and classes commonly used for verification☆50Updated 7 months ago