artecs-group / RVfpga-sim-addons
Recent updates and features added to the RVfpga course developed by Imagination Technologies.
☆14Updated this week
Alternatives and similar repositories for RVfpga-sim-addons:
Users that are interested in RVfpga-sim-addons are comparing it to the libraries listed below
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆64Updated last month
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆17Updated 2 years ago
- ☆25Updated 2 weeks ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 5 months ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆33Updated 4 years ago
- Open Source PHY v2☆27Updated 11 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- ☆33Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- ☆26Updated 4 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- Wraps the NVDLA project for Chipyard integration☆19Updated 2 weeks ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆32Updated last month
- APB UVC ported to Verilator☆11Updated last year
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆31Updated last month
- A reference book on System-on-Chip Design☆25Updated 11 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆45Updated 5 months ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆26Updated 6 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆48Updated 2 months ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated last year
- Open source RTL simulation acceleration on commodity hardware☆25Updated last year
- ☆10Updated last year
- Library of open source Process Design Kits (PDKs)☆37Updated last week
- SystemVerilog RTL Linter for YoSys☆20Updated 4 months ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago