aignacio / riscv_verilator_modelLinks
RISCV model for Verilator/FPGA targets
☆53Updated 5 years ago
Alternatives and similar repositories for riscv_verilator_model
Users that are interested in riscv_verilator_model are comparing it to the libraries listed below
Sorting:
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 5 months ago
- A simple DDR3 memory controller☆55Updated 2 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated 2 weeks ago
- RISC-V Nox core☆62Updated 2 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated last year
- Platform Level Interrupt Controller☆40Updated last year
- ☆58Updated 4 years ago
- Spen's Official OpenOCD Mirror☆50Updated 2 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆47Updated 7 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- Multi-Technology RAM with AHB3Lite interface☆23Updated last year
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆71Updated 2 years ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 4 months ago
- Mathematical Functions in Verilog☆92Updated 4 years ago
- General Purpose AXI Direct Memory Access☆50Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- ☆38Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆60Updated 4 months ago
- RISC-V Verification Interface☆92Updated 3 months ago
- Basic RISC-V Test SoC☆125Updated 6 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆82Updated 2 years ago
- RISC-V RV32IMAFC Core for MCU☆37Updated 4 months ago
- Generic FIFO implementation with optional FWFT☆57Updated 5 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago