aignacio / riscv_verilator_modelLinks
RISCV model for Verilator/FPGA targets
☆53Updated 5 years ago
Alternatives and similar repositories for riscv_verilator_model
Users that are interested in riscv_verilator_model are comparing it to the libraries listed below
Sorting:
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆46Updated 3 years ago
- Yet Another RISC-V Implementation☆96Updated 11 months ago
- Platform Level Interrupt Controller☆41Updated last year
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆119Updated last month
- SpinalHDL Hardware Math Library☆89Updated last year
- RISC-V Nox core☆68Updated last month
- Open-source high performance AXI4-based HyperRAM memory controller☆76Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 6 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 8 months ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 5 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- ☆40Updated last year
- Mathematical Functions in Verilog☆93Updated 4 years ago
- A simple DDR3 memory controller☆59Updated 2 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆99Updated 2 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 10 months ago
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- Multi-Technology RAM with AHB3Lite interface☆23Updated last year
- Ethernet MAC 10/100 Mbps☆85Updated 5 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆87Updated 2 years ago
- ☆59Updated 3 years ago
- Open source ISS and logic RISC-V 32 bit project☆57Updated 2 months ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆113Updated this week
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 6 months ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆139Updated last month
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆30Updated 4 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆123Updated 3 months ago