RISCV model for Verilator/FPGA targets
☆56Oct 17, 2019Updated 6 years ago
Alternatives and similar repositories for riscv_verilator_model
Users that are interested in riscv_verilator_model are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions☆21Dec 1, 2024Updated last year
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago
- JPEG Compression RTL implementation☆11Aug 19, 2017Updated 9 years ago
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆17Apr 12, 2020Updated 6 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆38Dec 24, 2024Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆14Nov 8, 2023Updated 2 years ago
- Projects using the Sipeed Tang Primer FPGA development board☆17Dec 6, 2020Updated 5 years ago
- ☆16Sep 26, 2022Updated 4 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Aug 9, 2026Updated last month
- Source code repo for UVM Tutorial for Candy Lovers☆14Apr 23, 2017Updated 9 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- Description of a RISC-V architecture based on MIPS 3000☆15Apr 24, 2023Updated 3 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆11Oct 17, 2019Updated 6 years ago
- RISC-V Virtual Prototype☆49Oct 1, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆36May 17, 2026Updated 4 months ago
- FPGA reference design for the the Swerv EH1 Core☆71Dec 10, 2019Updated 6 years ago
- ☆41Jan 23, 2024Updated 2 years ago
- Adding UVM support to Icarus Verilog (and Verilator in near future) by taking a step-by-step, bottom-up approach.☆24Dec 27, 2022Updated 3 years ago
- This project proposes a distributed communication protocol called MPIQ (Classical-Quantum Message Passing Interface) for the "classical +…☆15Apr 2, 2026Updated 6 months ago
- ☆15Jun 1, 2019Updated 7 years ago
- Generate UVM testbench framework template files with Python 3☆26Dec 23, 2019Updated 6 years ago
- Scripts to automate building linux images for my emulator riscv_em☆16Jul 27, 2026Updated 2 months ago
- Modified version of PULP Ara to support Vector Cryptography (Zvk) Instructions☆16Jan 21, 2026Updated 8 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆23Mar 8, 2024Updated 2 years ago
- ☆13Aug 22, 2022Updated 4 years ago
- Basic ISA prototype Card☆16Apr 13, 2019Updated 7 years ago
- Wrapper for Rocket-Chip on FPGAs☆140Oct 5, 2022Updated 4 years ago
- A small DNN library for RISC-V, using RISC-V Vector and Matrix extensions☆11Mar 13, 2025Updated last year
- SystemC to Verilog Synthesizable Subset Translator☆12May 12, 2023Updated 3 years ago
- Source code repo for UVM Tutorial for Candy Lovers☆210Apr 23, 2017Updated 9 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆31May 20, 2019Updated 7 years ago
- Scripts for using some ShaderToy shaders in GStreamer☆10Jun 16, 2018Updated 8 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- XNOR-Net, CUDNN5 supported version of XNOR-Net-caffe: https://github.com/loswensiana/BWN-XNOR-caffe☆32Apr 1, 2018Updated 8 years ago
- ECE 4551: Computer Architecture☆11Nov 25, 2019Updated 6 years ago
- VexRiscv-SMP integration test with LiteX.☆26Nov 16, 2020Updated 5 years ago
- Reverse Engineered Sigfox Stack - Library☆27May 3, 2021Updated 5 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆57Aug 1, 2026Updated 2 months ago
- Tool for code generation based on openvx graph representations. (THIS PROJECT IS NO LONGER MAINTAINED)☆10Dec 20, 2022Updated 3 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆36Aug 21, 2026Updated last month