A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple masters arbitration. Simulation waveforms are also included.
☆45Aug 10, 2022Updated 4 years ago
Alternatives and similar repositories for AXI4_Master_Interconnect_Slave
Users that are interested in AXI4_Master_Interconnect_Slave are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- AXI Interconnect☆59Aug 20, 2021Updated 5 years ago
- AXI总线连接器☆111Mar 26, 2020Updated 6 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆40Mar 13, 2025Updated last year
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated 2 years ago
- ☆35Jul 9, 2025Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Verification of an Asynchronous FIFO using UVM & SVA☆13Jun 26, 2025Updated last year
- Parametric AXI4 crossbar in SystemVerilog☆249May 25, 2026Updated 5 months ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Mar 17, 2022Updated 4 years ago
- ☆21Nov 18, 2022Updated 3 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆13Jul 14, 2024Updated 2 years ago
- The implemention & test code for xilinx fft ip core(v 9.0), standard AIX4, for future reference☆16Jul 14, 2019Updated 7 years ago
- Generic AXI interconnect fabric☆13Jul 17, 2014Updated 12 years ago
- Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…☆13Oct 8, 2017Updated 9 years ago
- Basic floating-point components for RISC-V processors☆12Aug 13, 2017Updated 9 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- commit rtl and build cosim env☆16Feb 15, 2024Updated 2 years ago
- UVM Testbench for synchronus fifo☆21Aug 28, 2020Updated 6 years ago
- Design a cache by using Verilog☆13Jan 12, 2017Updated 9 years ago
- IP core with AXI interface for reading the Device DNA from the PL of Zynq 7000 devices☆14Nov 25, 2021Updated 4 years ago
- Open Source SSD Controller. NVMe and Lightstor variants☆18May 21, 2014Updated 12 years ago
- Sample UVM code for axi ram dut☆40Dec 14, 2021Updated 4 years ago
- APB VIP (UVM)☆19Sep 6, 2018Updated 8 years ago
- AMBA bus lecture material☆562Jan 21, 2020Updated 6 years ago
- A Preprocessor for Verilog HDL written in C++☆11May 26, 2012Updated 14 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- axi video dma ip in verilog☆11Aug 22, 2020Updated 6 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆21Sep 14, 2023Updated 3 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆19Dec 12, 2025Updated 10 months ago
- 实现带有BD(Buffer Description缓存描述符)的四通道DMA控制器设计,每个通道包括配置寄存器模块,源端控制模 块,缓存模块和目的端控制模块☆12Sep 12, 2023Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆57Dec 6, 2023Updated 2 years ago
- ☆13Mar 10, 2023Updated 3 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- ☆14Nov 5, 2017Updated 8 years ago
- ☆90Jun 27, 2022Updated 4 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Implementation of the PCIe physical layer☆64Jul 11, 2025Updated last year
- Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)☆47Jun 7, 2017Updated 9 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- RTL and UVM test code of a Multi-NoC system☆12Dec 7, 2021Updated 4 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆248Jul 16, 2023Updated 3 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆26Mar 25, 2025Updated last year
- OpenExSys_NoC a mesh-based network on chip IP.☆21Dec 1, 2023Updated 2 years ago