Alternatives and similar repositories for AXI4_Master_Interconnect_Slave

Users that are interested in AXI4_Master_Interconnect_Slave are comparing it to the libraries listed below

• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆53Updated 4 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆41Updated 3 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆80Updated last year
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆96Updated 5 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 2 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆59Updated last year
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆107Updated 4 years ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆66Updated last year
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆64Updated 3 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆35Updated 2 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆69Updated 4 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆75Updated 11 years ago
• freecores / robust_axi2ahb
  Generic AXI to AHB bridge
  ☆17Updated 11 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆45Updated last year
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆79Updated 7 years ago
• freecores / apbi2c
  APB to I2C
  ☆43Updated 11 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆48Updated 2 months ago
• kuladeepsaireddy / OpenNoc
  ☆36Updated 6 years ago
• nahidrn / axi_vip_master
  Sample UVM code for axi ram dut
  ☆37Updated 3 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆104Updated 5 years ago
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆64Updated last year
• techvinodreddy / UART-IP-CORE16550A-Verification-UVM
  The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …
  ☆17Updated 4 years ago
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆26Updated 3 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆175Updated last month
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆56Updated 11 years ago
• Buddhimah / System-Bus-Design-Verilog
  This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
  ☆32Updated 5 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆77Updated 7 years ago
• prasadp4009 / 2-way-Set-Associative-Cache-Controller
  Synthesizable and Parameterized Cache Controller in Verilog
  ☆45Updated 2 years ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆34Updated 8 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆70Updated 4 years ago