Alternatives and similar repositories for ascon-hardware-sca

Users that are interested in ascon-hardware-sca are comparing it to the libraries listed below

• XBQ314 / A-Number-Theoretic-Transform-Accelerator-with-Two-Parallel-Simplified-Butterfly-Units
  Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现，基为2，有两个并行的蝶形单元
  ☆19Updated 3 years ago
• acmert / kyber-polmul-hw
  Hardware implementation of polynomial multiplication operation of CRYSTALS-KYBER PQC scheme
  ☆40Updated 4 years ago
• NikhilRout / NTT-FPGA
  Verilog Implementation of the Number Theoretic Transform (NTT) and its inverse operation (INTT) utilizing modulo arithmetic for lattice-b…
  ☆15Updated 2 months ago
• chipsalliance / adams-bridge
  Post-Quantum Cryptography IP Core (Crystals-Dilithium)
  ☆44Updated this week
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆42Updated 6 years ago
• rprimas / ascon-verilog
  Hardware Design of Ascon
  ☆37Updated 3 weeks ago
• KULeuven-COSIC / NTRU_NTT_HW
  ☆25Updated 4 years ago
• hadipourh / CryptoHDL
  A list of VHDL codes implementing cryptographic algorithms
  ☆27Updated 4 years ago
• mematrix / AES-FPGA
  AES加密解密算法的Verilog实现
  ☆69Updated 10 years ago
• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆33Updated 8 years ago
• momalab / CoPHEE
  CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
  ☆36Updated last year
• GMUCERG / Dilithium
  High-speed full CRYSTALS-DILITHIUM implementation on FPGA: Keygen, Sign, Verify.
  ☆75Updated 3 years ago
• scluconn / LPN-based_PUF
  FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.
  ☆15Updated 8 years ago
• lajanugen / Modular-Exponentiation
  Verilog Implementation of modular exponentiation using Montgomery multiplication
  ☆37Updated 11 years ago
• raymondrc / FPGA-SM3-HASH
  Description of Chinese SM3 Hash algorithm with Verilog HDL
  ☆52Updated 7 years ago
• chipsalliance / caliptra-ss
  HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
  ☆36Updated last week
• alibaba-damo-academy / damo_ctl_cham
  ☆27Updated 2 years ago
• p4r4xor / Montgomery1024
  Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation
  ☆13Updated 6 years ago
• xingyf14 / CRYSTALS-Kyber
  ☆59Updated 4 years ago
• acmert / parametric-ntt
  Parametric NTT/INTT Hardware Generator
  ☆80Updated 4 years ago
• kgpai94 / ECC-Encryption-System
  This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…
  ☆32Updated 7 years ago
• ascon / ascon-hardware
  NIST LWC Hardware Reference Implementation of Ascon v1.2
  ☆31Updated 2 years ago
• trivedidvijen / SPI-to-I2C-Protocol-Conversion-Using-Verilog
  SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.
  ☆12Updated 4 years ago
• zdszx / Modexpowering3
  a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier
  ☆25Updated 3 years ago
• raymondrc / FPGA_SM4
  FPGA implementation of Chinese SM4 encryption algorithm.
  ☆57Updated 7 years ago
• kemalderya / pqc-param-ntt
  ☆27Updated 4 years ago
• pulp-platform / obi
  OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
  ☆19Updated last month
• Elrori / 4096bit-IDDMM-Verilog
  4096bit Iterative digit-digit Montgomery Multiplication in Verilog
  ☆18Updated 3 years ago
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆24Updated last year
• secworks / trng
  True Random Number Generator core implemented in Verilog.
  ☆79Updated 5 years ago