This repository contains source code that is aimed at converting a Spice NetList to its corresponding layout.
☆27Mar 29, 2021Updated 5 years ago
Alternatives and similar repositories for vsdGraphExtractor
Users that are interested in vsdGraphExtractor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆21Nov 22, 2021Updated 4 years ago
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Oct 18, 2021Updated 4 years ago
- ☆41Feb 28, 2022Updated 4 years ago
- Optimal gate sizing of digital circuits using geometric programming☆11Aug 18, 2016Updated 9 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆18Oct 16, 2021Updated 4 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- ☆14May 11, 2022Updated 4 years ago
- acst - Analog Circuit Synthesis Tool☆21Jan 15, 2022Updated 4 years ago
- ☆377Updated this week
- A collection of design automation algorithms, methodologies, and tools for electronics/photonics, and emerging eda technologies☆19Apr 1, 2023Updated 3 years ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆17Dec 8, 2020Updated 5 years ago
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆17Mar 31, 2021Updated 5 years ago
- A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …☆34Aug 21, 2024Updated last year
- SRAM☆24Sep 6, 2020Updated 5 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆33Nov 13, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Repository for VSD-IAT Workshop: Physical Verification using SKY130☆10Aug 15, 2021Updated 4 years ago
- SMT-based-STDCELL-Layout-Generator☆20Sep 30, 2021Updated 4 years ago
- Simple and most probably incomplete parser for spectre netlists☆14Oct 4, 2016Updated 9 years ago
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆21Dec 15, 2020Updated 5 years ago
- 8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving…☆15Jul 21, 2022Updated 4 years ago
- EDA physical synthesis optimization kit☆69Nov 13, 2023Updated 2 years ago
- Fluid Pipelines☆11May 4, 2018Updated 8 years ago
- Open stadard cell library for open 28nm process☆17Jul 5, 2023Updated 3 years ago
- Arche is a Greek word with primary senses "beginning". The repository defines a framework for technology mapping of emerging technologies…☆11May 15, 2020Updated 6 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆32Jul 30, 2022Updated 4 years ago
- Machine Generated Analog IC Layout☆293Apr 24, 2024Updated 2 years ago
- SIMPLER MAGIC: Synthesis and In-memory MaPping of Logic Execution in a single Row for Memristor Aided loGIC☆13Dec 5, 2019Updated 6 years ago
- Data Structures and Algorithms. Contribute and Learn together.☆11Oct 11, 2022Updated 3 years ago
- Arbitrary Cell Generator enables parametrized grid-free circuit layout creation☆17Jun 1, 2020Updated 6 years ago
- Code for new techniques of VLSI placement☆13Oct 11, 2013Updated 12 years ago
- A LTSPICE like circuit simulation software, base on Qt☆30Mar 14, 2020Updated 6 years ago
- Combination of Analog Circuit Sizing and DL.☆18Mar 24, 2023Updated 3 years ago
- Files for Advanced Integrated Circuits☆44Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Automatically exported from code.google.com/p/eqntott☆15Sep 23, 2015Updated 10 years ago
- 1G‑style Ethernet PHY PCS block in Sky130 using OpenLane☆18Feb 15, 2026Updated 5 months ago
- Magic VLSI Layout Tool☆21Oct 10, 2019Updated 6 years ago
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆65Jul 22, 2026Updated 2 weeks ago
- ☆13Apr 22, 2021Updated 5 years ago
- Problem B: 3D Placement with D2D Vertical Connections☆11Jun 30, 2022Updated 4 years ago
- Providing examples on how to setup and use xschem, ngspice, and gaw, to do analog IC design☆15Jul 6, 2025Updated last year