sayden / verilog-tutorials
☆12Updated 8 years ago
Alternatives and similar repositories for verilog-tutorials
Users that are interested in verilog-tutorials are comparing it to the libraries listed below
Sorting:
- Complete tutorial code.☆20Updated last year
- Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.☆58Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- ☆29Updated last year
- ☆16Updated 2 years ago
- This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop☆36Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- Summer School Week 1 & 2 repo☆11Updated 2 years ago
- ☆22Updated 6 months ago
- SoC design & prototyping☆13Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆47Updated 4 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆68Updated 4 years ago
- System Verilog BootCamp☆24Updated 3 years ago
- Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)☆43Updated 7 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆9Updated 3 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆62Updated 8 years ago
- ☆41Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆69Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆91Updated this week
- Open source ISS and logic RISC-V 32 bit project☆52Updated 3 weeks ago
- Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer☆31Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- RISCV model for Verilator/FPGA targets☆52Updated 5 years ago
- General Purpose AXI Direct Memory Access☆49Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆57Updated 2 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆29Updated 4 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆30Updated 3 years ago