Alternatives and similar repositories for verilog-tutorials

Users that are interested in verilog-tutorials are comparing it to the libraries listed below

• ashishrana160796 / verilog-starter-tutorials
  Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
  ☆61Updated 5 years ago
• AleksandarKostovic / SystemC-tutorial
  Brief SystemC getting started tutorial
  ☆96Updated 6 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆69Updated 11 months ago
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆79Updated 2 years ago
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆26Updated 7 years ago
• embedded-explorer / Open-Source-RTL-Design
  This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop
  ☆40Updated 4 years ago
• Suntrakanesh / System-Verilog-bootcamp
  System Verilog BootCamp
  ☆25Updated 4 years ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• Muriukidavid / systemc-examples
  A repository for SystemC Learning examples
  ☆73Updated 3 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆60Updated last week
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆44Updated 11 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 6 years ago
• A-T-Kristensen / simple-alu-uvm
  This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit
  ☆27Updated 7 years ago
• Rishabh-zhcet / Analog-to-Digital-Converter
  This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …
  ☆11Updated 3 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆61Updated 3 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆43Updated 4 years ago
• SimpleCPU / SimpleCPU
  An open source CPU design and verification platform for academia
  ☆115Updated 5 months ago
• JeffDeCola / my-verilog-examples
  A place to keep my synthesizable verilog examples.
  ☆50Updated 9 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆81Updated 3 weeks ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆83Updated 4 years ago
• learnwithexamples / learnsystemc
  Learn systemC with examples
  ☆130Updated 3 years ago
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆66Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 7 months ago
• verilator / example-systemverilog
  ☆40Updated 2 years ago
• martinriis / RISC-V-Vector-Processor
  256-bit vector processor based on the RISC-V vector (V) extension
  ☆31Updated 4 years ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆82Updated last month
• RClabiisc / I2SRV32-V-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆32Updated last year
• Stuart-Swan / Matchlib-Examples-Kit-For-Accellera-Synthesis-WG
  ☆12Updated this week
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆129Updated last week
• learn-cocotb / tutorial
  Complete tutorial code.
  ☆23Updated last year