vsdip / avsddac_3v3_sky130_v1
☆12Updated 2 years ago
Alternatives and similar repositories for avsddac_3v3_sky130_v1:
Users that are interested in avsddac_3v3_sky130_v1 are comparing it to the libraries listed below
- ☆40Updated 2 years ago
- PLL Designs on Skywater 130nm MPW☆20Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- Analog and power building blocks for sky130 pdk☆20Updated 3 years ago
- ☆16Updated 2 years ago
- ☆19Updated last year
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆15Updated 5 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆38Updated 6 months ago
- A 10bit SAR ADC in Sky130☆22Updated 2 years ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆11Updated 4 years ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆59Updated this week
- repository for a bandgap voltage reference in SKY130 technology☆35Updated 2 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆64Updated 4 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆37Updated 2 years ago
- ☆10Updated 3 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆14Updated 4 years ago
- ☆45Updated last month
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆42Updated 4 years ago
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆8Updated 11 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆64Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆36Updated 3 years ago
- ☆20Updated 3 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆21Updated 5 years ago
- Parasitic capacitance analysis of foundry metal stackups☆10Updated 4 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆41Updated 3 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆51Updated 2 years ago
- ☆33Updated 2 months ago
- Skywaters 130nm Klayout PDK☆21Updated this week