Alternatives and similar repositories for Pill

Users that are interested in Pill are comparing it to the libraries listed below

• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆126Updated last week
• Vlsir / Vlsir
  Interchange formats for chip design.
  ☆36Updated 6 months ago
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆54Updated 2 years ago
• patrickschulz / openPCells
  Parametric layout generator for digital, analog and mixed-signal integrated circuits
  ☆61Updated this week
• eskiyerli / revolution-eda
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆52Updated this week
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆88Updated 7 months ago
• efabless / cace
  Circuit Automatic Characterization Engine
  ☆50Updated 9 months ago
• efabless / mpw_precheck
  ☆43Updated 8 months ago
• aidangoettsch / asg
  An automatic schematic generation tool which generates schematics from a SPICE netlist, usually of output from qflow.
  ☆29Updated 5 years ago
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆40Updated 3 months ago
• MatBucher / ekv3model
  ☆19Updated last year
• dwarning / VA-Models
  Verilog-A simulation models
  ☆86Updated 3 weeks ago
• idea-fasoc / fasoc
  ☆56Updated 2 years ago
• DDD-FIT-CTU / CMOS-SPICE-Model-Collections
  MOSIS MPW Test Data and SPICE Models Collections
  ☆38Updated 5 years ago
• johnkustin / bandgapReferenceCircuit
  repository for a bandgap voltage reference in SKY130 technology
  ☆41Updated 2 years ago
• The-OpenROAD-Project / OpenRCX
  ☆22Updated 4 years ago
• mbalestrini / gdsiistl
  Converts GDSII files to STL files.
  ☆39Updated last year
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆47Updated last year
• ashwith / pyMOSChar
  Python port of Prof. Boris Murmann's gm/ID Starter Kit
  ☆54Updated 8 years ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆75Updated last month
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 7 months ago
• laurentc2 / SKY130_for_KLayout
  KLayout technology files for Skywater SKY130
  ☆42Updated 2 years ago
• ACMmodel / MOSFET_model
  A simple MOSFET model with only 5-DC-parameters for circuit simulation
  ☆49Updated 2 months ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆54Updated 2 years ago
• StefanSchippers / xschem_sky130
  XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
  ☆66Updated 2 months ago
• laurentc2 / ASAP7_for_KLayout
  KLayout technology files for ASAP7 FinFET educational process
  ☆23Updated 2 years ago
• mabrains / sky130_klayout_pdk
  Skywater 130nm Klayout Device Generators PDK
  ☆31Updated last year
• niftylab / laygo2
  LAYout with Gridded Objects v2
  ☆65Updated 5 months ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated last week