Skill language interpreter
☆73Aug 24, 2020Updated 5 years ago
Alternatives and similar repositories for Pill
Users that are interested in Pill are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Cadence Virtuoso Git Integration written in SKILL++☆162Sep 3, 2022Updated 3 years ago
- Reads a Cadence techfile into KLayout and produces layer properties from it☆30Oct 22, 2023Updated 2 years ago
- A C++ VLSI circuit schematic and layout database library☆15Jul 1, 2024Updated last year
- Top level CedarEDA integration package☆28Oct 22, 2024Updated last year
- MOSIS MPW Test Data and SPICE Models Collections☆42Apr 2, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Skywater 130nm Klayout Device Generators PDK☆30Jul 12, 2024Updated last year
- A seamless python to Cadence Virtuoso Skill interface☆299Mar 23, 2026Updated last month
- Intel's Analog Detailed Router☆42Jul 18, 2019Updated 6 years ago
- my cadence/virtuoso/icfb skill functions develloped over the years☆156Mar 27, 2026Updated last month
- Jupyter kernel for Cadence SKILL☆22Feb 16, 2017Updated 9 years ago
- Sandbox for experimenting with Ngspice and open PDKs in Google Colab☆32Jun 5, 2024Updated last year
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆74Apr 23, 2026Updated last week
- Primitives for GF180MCU provided by GlobalFoundries.☆57Aug 28, 2023Updated 2 years ago
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Aug 31, 2018Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This library is a low level parser for the OpenAccess file format.☆16Jun 24, 2017Updated 8 years ago
- Interchange formats for chip design.☆38Feb 15, 2026Updated 2 months ago
- ADMS is a code generator for some of Verilog-A☆103Nov 28, 2022Updated 3 years ago
- Verilog-A implementation of MOSFET model BSIM4.8☆15Oct 4, 2019Updated 6 years ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆132Apr 4, 2026Updated 3 weeks ago
- SKILL Codes, PCell Creation☆20May 21, 2021Updated 4 years ago
- Verilog-A simulation models☆100Feb 24, 2026Updated 2 months ago
- tools regarding on analog modeling, validation, and generation☆22Apr 11, 2023Updated 3 years ago
- USB Full-Speed core written in migen/LiteX☆12Sep 19, 2019Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆21Nov 22, 2021Updated 4 years ago
- LAYout with Gridded Objects☆34Jun 18, 2020Updated 5 years ago
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆26Mar 11, 2023Updated 3 years ago
- ☆45Feb 25, 2025Updated last year
- An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics☆15Updated this week
- Inter Process Communication (IPC) between Python and Cadence Virtuoso☆83Dec 22, 2016Updated 9 years ago
- Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.☆57Apr 9, 2026Updated 3 weeks ago
- Python interface for Cadence Spectre☆28Feb 17, 2026Updated 2 months ago
- KLayoutPhotonicPCells Core Library. Functionallities to extend KLayout PCells for Photonics☆10Jan 10, 2020Updated 6 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Hardware Description Library☆93Feb 17, 2026Updated 2 months ago
- Utilities for working with Cadence's SKILL/SKILL++ including a unit testing framework.☆48Nov 6, 2020Updated 5 years ago
- A port of the Cells extension to CLOS to Python.☆13Apr 20, 2016Updated 10 years ago
- LAYout with Gridded Objects v2☆67Jun 22, 2025Updated 10 months ago
- XicTools: Xic graphical editor, WRspice circuit simulator, and accessories. for electronic design.☆181Nov 17, 2025Updated 5 months ago
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Sep 24, 2021Updated 4 years ago
- Yosys plugin for synthesis of Bluespec code☆15Sep 8, 2021Updated 4 years ago