Compiler Explorer for RTL: synthesize Verilog with Yosys and explore timing paths, logic depth, and fanin/fanout interactively
☆44Sep 10, 2026Updated last week
Alternatives and similar repositories for synth-explorer
Users that are interested in synth-explorer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆10Oct 15, 2021Updated 4 years ago
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- A collection of datapath circuit design and verification benchmarks☆19Aug 24, 2026Updated 3 weeks ago
- Yosys plugin for logic locking and supply-chain security☆25Apr 5, 2025Updated last year
- A bit-serial CPU☆20Sep 29, 2019Updated 6 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Digital Design Equivalence Checking☆109Updated this week
- ☆23Mar 12, 2026Updated 6 months ago
- A collection of commonly asked RTL design interview questions☆61May 2, 2017Updated 9 years ago
- ☆12Jun 4, 2021Updated 5 years ago
- Pulse is a multi-platform digital logic simulation engine for VHDL made with C++. It transforms VHDL source code into logic components so…☆87Updated this week
- AI assisted Shell, aka "Ash". Wraps around your existing shell and brings AI-LLM to the CLI for analyzing EDA files.☆29Apr 6, 2026Updated 5 months ago
- ☆14Jun 21, 2026Updated 2 months ago
- A minimal neuromorphic chip design in SystemVerilog to learn how brain-inspired computing works from the ground up.☆29Mar 30, 2026Updated 5 months ago
- CIRCT and Yosys interoperability, demonstrated with CHISEL☆18Feb 3, 2026Updated 7 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Benchmarks for Approximate Circuit Synthesis☆17Aug 2, 2020Updated 6 years ago
- ☆25Jun 23, 2024Updated 2 years ago
- ☆21Nov 18, 2022Updated 3 years ago
- APS: An open-source toolchain towards agile processor specialization based on MLIR☆21Jan 17, 2026Updated 8 months ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆25Nov 9, 2025Updated 10 months ago
- FPGA synthesis tool powered by equality saturation and program synthesis.☆14Jan 9, 2026Updated 8 months ago
- RTLMeter benchmark suite☆33Updated this week
- PCIe stack written in Amaranth.☆18Apr 27, 2026Updated 4 months ago
- WAL enables programmable waveform analysis.☆185Aug 16, 2026Updated last month
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ideas and eda software for vlsi design☆51Updated this week
- Example project for the BRS-100-GW1NR9 FPGA development board.☆19Sep 9, 2026Updated last week
- ☆18Jul 9, 2025Updated last year
- Constrained random stimuli generation for C++ and SystemC☆11Nov 1, 2016Updated 9 years ago
- SystemVerilog file list pruner☆19Updated this week
- Project Peppercorn GateMate Test Cases☆17Feb 25, 2026Updated 6 months ago
- ☆13Jan 20, 2023Updated 3 years ago
- ☆30Jun 25, 2024Updated 2 years ago
- FPGA code for NeTV2☆16Dec 3, 2018Updated 7 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- micro version of cocotb, to run on microcontrollers or desktop to get hardware in the loop☆26Feb 25, 2025Updated last year
- ElemRV - End-to-end Open-Source RISC-V Microcontroller☆145Updated this week
- fast probabilistic symmetry detection on graphs☆22Aug 13, 2026Updated last month
- RTL implementation of a ray-tracing GPU☆17Dec 18, 2012Updated 13 years ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated 2 years ago
- VS Code extension for SystemVerilog design navigation, RTL tracing, schematic viewer, and waveform integration☆61Jul 25, 2026Updated last month
- A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector (th…☆25Jun 29, 2026Updated 2 months ago