Alternatives and similar repositories for cocotb-test

Users that are interested in cocotb-test are comparing it to the libraries listed below

• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆32Updated 4 months ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆48Updated 2 years ago
• schang412 / cocotbext-spi
  ☆27Updated last month
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆32Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 6 months ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆55Updated last year
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆27Updated last year
• AsFigo / svck
  ☆14Updated 7 months ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆16Updated 2 weeks ago
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 6 months ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆53Updated 2 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 3 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆54Updated last week
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆57Updated 6 years ago
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆26Updated 4 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 8 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆82Updated last month
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆73Updated 4 months ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated 2 months ago
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆60Updated 2 years ago
• vsdip / vsdsram_sky130
  ☆41Updated 3 years ago
• mcjtag / axis-uart
  AXI Stream UART (verilog)
  ☆12Updated 6 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 4 years ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 5 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆42Updated 3 months ago
• mciepluc / apbi2c_cocotb_example
  An example Python-based MDV testbench for apbi2c core
  ☆30Updated last year
• wallento / cocotbext-uart
  UART cocotb module
  ☆11Updated 4 years ago