Alternatives and similar repositories for cocotb-test

Users that are interested in cocotb-test are comparing it to the libraries listed below

• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆32Updated 3 months ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆30Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 5 months ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆48Updated last year
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 7 months ago
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 5 months ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆55Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆72Updated 3 months ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆56Updated 5 years ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated 2 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆52Updated last week
• AsFigo / svck
  ☆14Updated 7 months ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆15Updated this week
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆26Updated last year
• pulp-platform / svase
  ☆33Updated 11 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆79Updated 2 weeks ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆33Updated last year
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆63Updated 3 weeks ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 10 months ago
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆46Updated 2 weeks ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• schang412 / cocotbext-spi
  ☆27Updated 2 weeks ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 5 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆53Updated 2 years ago
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆26Updated 4 years ago
• alexforencich / cocotbext-i2c
  I2C models for cocotb
  ☆38Updated 3 months ago
• vsdip / vsdsram_sky130
  ☆43Updated 3 years ago
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆12Updated 4 months ago